Primitives to enhance thread-level speculation

Abstract

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

What is claimed is: 
     
         1 . A processor, comprising:
 decode logic configured to receive a first instruction and a second instruction and to decode whether the first instruction includes a first prefix and the second instruction includes a second prefix;   execution logic coupled to the decode logic to execute a critical section demarcated by the first instruction and the second instruction without acquiring a hardware critical section lock if the first instruction includes the first prefix and the second instruction includes the second prefix, the execution logic to acquire the hardware critical section lock prior to executing the critical section if the first instruction does not includes the first prefix or the second instruction does not includes the second prefix;   buffer logic coupled to the execution logic to buffer memory updates from the critical section during the execution of the critical section; and   commit logic coupled to the buffer logic to commit the memory updates to memory in response to the second instruction.   
     
     
         2 . The processor of  claim 1 , further comprising monitor logic associated with the buffer logic to track contention from other threads to memory locations accessed during the execution logic speculatively executing the critical section, wherein the memory updates are committed when there is no memory contention from other threads. 
     
     
         3 . The processor of  claim 2 , wherein the buffer logic includes a cache memory configured to hold the memory updates as buffered updates and the monitor logic includes attributes associated with the cache memory to track accesses during the execution logic executing the critical section and to track contention from other threads. 
     
     
         4 . The processor of  claim 1 , wherein the first instruction is to write a first value to a first memory location that is shared by one or more other threads, and wherein the second instruction is to write a second value to a second memory location that is shared by the one or more other threads. 
     
     
         5 . The processor of  claim 1 , wherein first instruction includes a lock acquire instruction with a first atomic prefix appended to the lock acquire instruction and the second instruction includes a lock release instruction with a second atomic prefix appended to the lock release instruction. 
     
     
         6 . The processor of  claim 5 , wherein the execution logic is configured not to execute the lock acquire instruction in response to the first instruction including the first atomic prefix and not to execute the lock release instruction in response to the second instruction including the second atomic prefix. 
     
     
         7 . The processor of  claim 1 , wherein the first instruction includes a first store instruction with a first atomic prefix appended to the first store instruction and the second instruction includes a second store instruction with a second atomic prefix appended to the second store instruction. 
     
     
         8 . A method, comprising:
 receiving a first instruction and a second instruction at a processor;   decoding, by a decode logic of the processor, whether the first instruction includes a first prefix and the second instruction includes a second prefix;   executing, by execution logic of the processor, a critical section demarcated by the first instruction and the second instruction without acquiring a hardware critical section lock if the first instruction includes the first prefix and the second instruction includes the second prefix, the execution logic to acquire the hardware critical section lock prior to executing the critical section if the first instruction does not includes the first prefix or the second instruction does not includes the second prefix;   buffering, by buffer logic of the processor, memory updates from the critical section during the execution of the critical section; and   committing, by commit logic of the processor the memory updates to memory in response to the second instruction.   
     
     
         9 . The method of  claim 8 , further comprising monitoring contention from other threads to memory locations accessed during the execution logic speculatively executing the critical section, wherein the memory updates are committed when there is no memory contention from other threads. 
     
     
         10 . The method of  claim 9 , wherein the buffer logic includes a cache memory configured to hold the memory updates as buffered updates and the monitor logic includes attributes associated with the cache memory to track accesses during the execution logic executing the critical section and to track contention from other threads. 
     
     
         11 . The method of  claim 8 , wherein the first instruction is to write a first value to a first memory location that is shared by one or more other threads, and wherein the second instruction is to write a second value to a second memory location that is shared by the one or more other threads. 
     
     
         12 . The method of  claim 8 , wherein first instruction includes a lock acquire instruction with a first atomic prefix appended to the lock acquire instruction and the second instruction includes a lock release instruction with a second atomic prefix appended to the lock release instruction. 
     
     
         13 . The method of  claim 12 , wherein the execution logic is configured not to execute the lock acquire instruction in response to the first instruction including the first atomic prefix and not to execute the lock release instruction in response to the second instruction including the second atomic prefix. 
     
     
         14 . The method of  claim 8 , wherein the first instruction includes a first store instruction with a first atomic prefix appended to the first store instruction and the second instruction includes a second store instruction with a second atomic prefix appended to the second store instruction. 
     
     
         15 . A system comprising:
 a processor including
 decode logic configured to receive a first instruction and a second instruction and to decode whether the first instruction includes a first prefix and the second instruction includes a second prefix, 
 execution logic coupled to the decode logic to execute a critical section demarcated by the first instruction and the second instruction without acquiring a hardware critical section lock if the first instruction includes the first prefix and the second instruction includes the second prefix, the execution logic to acquire the hardware critical section lock prior to executing the critical section if the first instruction does not includes the first prefix or the second instruction does not includes the second prefix, 
 buffer logic coupled to the execution logic to buffer memory updates from the critical section during the execution of the critical section, and 
 commit logic coupled to the buffer logic to commit the memory updates to memory in response to the second instruction; and 
   a memory coupled to the processor, the memory configured to hold at least the first instruction and the second instruction.   
     
     
         16 . The system of  claim 15 , wherein the processor further comprises monitor logic associated with the buffer logic to track contention from other threads to memory locations accessed during the execution logic speculatively executing the critical section, wherein the memory updates are committed when there is no memory contention from other threads. 
     
     
         17 . The system of  claim 16 , wherein the buffer logic includes a cache memory configured to hold the memory updates as buffered updates and the monitor logic includes attributes associated with the cache memory to track accesses during the execution logic executing the critical section and to track contention from other threads. 
     
     
         18 . The system of  claim 15 , wherein the first instruction is to write a first value to a first memory location that is shared by one or more other threads, and wherein the second instruction is to write a second value to a second memory location that is shared by the one or more other threads. 
     
     
         19 . The system of  claim 15 , wherein first instruction includes a lock acquire instruction with a first atomic prefix appended to the lock acquire instruction and the second instruction includes a lock release instruction with a second atomic prefix appended to the lock release instruction. 
     
     
         20 . The system of  claim 19 , wherein the execution logic is configured not to execute the lock acquire instruction in response to the first instruction including the first atomic prefix and not to execute the lock release instruction in response to the second instruction including the second atomic prefix. 
     
     
         21 . The system of  claim 15 , wherein the first instruction includes a first store instruction with a first atomic prefix appended to the first store instruction and the second instruction includes a second store instruction with a second atomic prefix appended to the second store instruction.