Inventor · disambiguated record
Shivnandan Kaushik
Also filed as: KAUSHIK SHIVNANDAN · KAUSHIK SHIVNANDAN D
50 granted patents·11 pending applications·785 citations·filing 1999–2023
98Inventor score
Top patents by PatentIndex Score
61 records- 0197US7882339B2Primitives to enhance thread-level speculationINTEL CORP·Filed 2005·Granted Feb 1, 2011·56 cites·11 claims
- 0297US7546487B2OS and firmware coordinated error handling using transparent firmware intercept and firmware servicesINTEL CORP·Filed 2005·Granted Jun 9, 2009·85 cites·13 claims
- 0396US7328293B2Queued locks using monitor-memory waitINTEL CORP·Filed 2007·Granted Feb 5, 2008·47 cites·21 claims
- 0491US9043521B2Technique for communicating interrupts in a computer systemINTEL CORP·Filed 2012·Granted May 26, 2015·18 cites·20 claims
- 0591US7191349B2Mechanism for processor power state aware distribution of lowest priority interruptINTEL CORP·Filed 2002·Granted Mar 13, 2007·59 cites·36 claims
- 0690US7117311B1Hot plug cache coherent interface method and apparatusINTEL CORP·Filed 2001·Granted Oct 3, 2006·59 cites·26 claims
- 0789US7627706B2Creation of logical APIC ID with cluster ID and intra-cluster IDINTEL CORP·Filed 2007·Granted Dec 1, 2009·22 cites·22 claims
- 0888US9990206B2Mechanism for instruction set based thread execution of a plurality of instruction sequencersINTEL CORP·Filed 2013·Granted Jun 5, 2018·8 cites·18 claims
- 0988US7769938B2Processor selection for an interrupt identifying a processor clusterINTEL CORP·Filed 2007·Granted Aug 3, 2010·18 cites·22 claims
- 1087US8479217B2Apparatus, system, and method for persistent user-level threadCHINYA GAUTHAM·Filed 2011·Granted Jul 2, 2013·7 cites·19 claims
- 1187US8010969B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2005·Granted Aug 30, 2011·16 cites·32 claims
- 1286US8032681B2Processor selection for an interrupt based on willingness to accept the interrupt and on priorityINTEL CORP·Filed 2007·Granted Oct 4, 2011·15 cites·19 claims
- 1386US7146514B2Determining target operating frequencies for a multiprocessor systemINTEL CORP·Filed 2003·Granted Dec 5, 2006·64 cites·26 claims
- 1485US7743233B2Sequencer address managementINTEL CORP·Filed 2005·Granted Jun 22, 2010·15 cites·21 claims
- 1584US7640384B2Queued locks using monitor-memory waitINTEL CORP·Filed 2007·Granted Dec 29, 2009·10 cites·21 claims
- 1683US7822900B2Apparatus and method for enumeration of processors during hot-plug of a compute nodeINTEL CORP·Filed 2008·Granted Oct 26, 2010·10 cites·20 claims
- 1780US7213093B2Queued locks using monitor-memory waitINTEL CORP·Filed 2003·Granted May 1, 2007·22 cites·14 claims
- 1880US6920581B2Method and apparatus for functional redundancy check mode recoveryINTEL CORP·Filed 2002·Granted Jul 19, 2005·29 cites·24 claims
- 1979US8516483B2Transparent support for operating system services for a sequestered sequencerCHINYA GAUTHAM·Filed 2005·Granted Aug 20, 2013·10 cites·26 claims
- 2079US7673090B2Hot plug interface control method and apparatusINTEL CORP·Filed 2001·Granted Mar 2, 2010·28 cites·27 claims
- 2178US8312198B2Technique for communicating interrupts in a computer systemTIRUVALLUR KESHAVAN·Filed 2012·Granted Nov 13, 2012·5 cites·24 claims
- 2278US7117396B2Scalable CPU error recorderINTEL CORP·Filed 2001·Granted Oct 3, 2006·26 cites·26 claims
- 2377US7761720B2Mechanism for processor power state aware distribution of lowest priority interruptsINTEL CORP·Filed 2007·Granted Jul 20, 2010·7 cites·22 claims
- 2474US8028295B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2005·Granted Sep 27, 2011·4 cites·21 claims
- 2574US7315952B2Power state coordination between devices sharing power-managed resourcesINTEL CORP·Filed 2004·Granted Jan 1, 2008·19 cites·29 claims
- 2674US6917999B2Platform and method for initializing components within hot-plugged nodesINTEL CORP·Filed 2001·Granted Jul 12, 2005·20 cites·25 claims
- 2773US8719819B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2005·Granted May 6, 2014·4 cites·20 claims
- 2873US8171268B2Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectorsNEWBURN CHRIS J·Filed 2005·Granted May 1, 2012·7 cites·5 claims
- 2973US7493438B2Apparatus and method for enumeration of processors during hot-plug of a compute nodeINTEL CORP·Filed 2001·Granted Feb 17, 2009·15 cites·29 claims
- 3072US7000102B2Platform and method for supporting hibernate operationsINTEL CORP·Filed 2001·Granted Feb 14, 2006·17 cites·17 claims
- 3169US8332619B2Primitives to enhance thread-level speculationJACOBSON QUINN A·Filed 2011·Granted Dec 11, 2012·2 cites·12 claims
- 3268US8887174B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersHANKINS RICHARD A·Filed 2011·Granted Nov 11, 2014·2 cites·10 claims
- 3368US7272741B2Hardware coordination of power management activitiesINTEL CORP·Filed 2004·Granted Sep 18, 2007·13 cites·31 claims
- 3467US12474848B2Techniques for memory resource control using memory resource partitioning and monitoringAMPERE COMPUTING LLC·Filed 2023·Granted Nov 18, 2025·0 cites·20 claims
- 3566US7360103B2P-state feedback to operating system with hardware coordinationINTEL CORP·Filed 2004·Granted Apr 15, 2008·14 cites·48 claims
- 3665US9069605B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionINTEL CORP·Filed 2013·Granted Jun 30, 2015·1 cites·20 claims
- 3761US6857066B2Apparatus and method to identify the maximum operating frequency of a processorINTEL CORP·Filed 2001·Granted Feb 15, 2005·7 cites·30 claims
- 3860US9875102B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2016·Granted Jan 23, 2018·0 cites·20 claims
- 3959US9766891B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2016·Granted Sep 19, 2017·0 cites·20 claims
- 4059US2017010895A1Mechanism for instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2016·Application pending·0 cites
- 4157US11966750B2System-on-chip management controllerAMPERE COMPUTING LLC·Filed 2022·Granted Apr 23, 2024·0 cites·20 claims
- 4257US10452403B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2015·Granted Oct 22, 2019·0 cites·16 claims
- 4357US9383997B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2013·Granted Jul 5, 2016·0 cites·20 claims
- 4456US7979699B2Processing capacity on demandINTEL CORP·Filed 2004·Granted Jul 12, 2011·4 cites·9 claims
- 4555US9720697B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2012·Granted Aug 1, 2017·0 cites·18 claims
- 4653US11977638B2Low-impact firmware updateAMPERE COMPUTING LLC·Filed 2022·Granted May 7, 2024·0 cites·20 claims
- 4753US8607235B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionHANKINS RICHARD A·Filed 2004·Granted Dec 10, 2013·3 cites·34 claims
- 4853US2025110902A1Processors employing default tags for writes to memory from devices not compliant with a memory tagging extension and related methodsAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 4952US8984199B2Inter-processor interruptsHAMMARLUND PER·Filed 2003·Granted Mar 17, 2015·5 cites·15 claims
- 5051US2013073835A1Primitives to enhance thread-level speculationJACOBSON QUINN A·Filed 2012·Application pending·0 cites
Showing the top 50 of 61 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →