Primitives to enhance thread-level speculation

Abstract

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

1 . An apparatus, comprising:
 a plurality of thread units to concurrently execute a plurality of threads;   a control storage area associated with a thread unit of the plurality of threads units, the control storage area to include a direct update field, wherein the control storage area is capable of being updated in response to execution of a user-level instruction;   a memory buffer storage area to hold data for a memory write instruction encountered during execution associated with the thread in response to the direct update field holding a monitor value to indicate writes are to be monitored.   
     
     
         2 . The apparatus of  claim 1 , further comprising a memory, wherein the data for the memory write instruction is to bypass the memory buffer storage area and be directly written to the memory in response to the direct update field holding an unmonitored value to indicate writes are not to be monitored. 
     
     
         3 . The apparatus of  claim 2 , wherein: the user-level instruction includes a Transaction Set (TRNXSET) instruction, when executed, to update the control storage area, wherein in response to a start of a critical section, the TRNXSET instruction is to be executed to update the direct update field to the monitored value and in response to an end of the critical section, the TRNXSET instruction is to be executed to update the direct update field to the unmonitored value. 
     
     
         4 . The apparatus of  claim 3 , wherein: the control storage area is further to include a reset field, wherein the memory buffer storage area is to be reset in response to the reset field holding a reset value. 
     
     
         5 . The apparatus of  claim 1 , further comprising:
 a memory address storage area to maintain an address of a memory read instruction encountered during execution associated with the thread in response to the direct update field holding the monitor value to indicate reads are to be monitored.   
     
     
         6 . The apparatus of  claim 2 , further comprising:
 logic to perform an atomic update from the memory buffer storage area to the memory in response to a transaction commit operation responsive to an atomic block of instructions including the memory write instruction have successfully executed.   
     
     
         7 . The apparatus of  claim 6 , further comprising a user-visible status storage area to include a transaction failure field to hold a failure value in response to a transaction failure event occurring. 
     
     
         8 . The apparatus of  claim 7 , wherein in response to resuming execution after encountering a trap during execution of the atomic block, execution of the atomic block resumes in response to the transaction failure field holding a non-failure value. 
     
     
         9 . A method, comprising:
 executing an update control register user-level instruction to update a control register associated with a speculative thread of a processor to hold a monitor value;   executing with the speculative thread a memory instruction;   monitoring the memory instruction in response to the control register associated with the speculative thread holding the monitor value; and   not monitoring the memory instruction in response to the control register holding an unmonitored value.   
     
     
         10 . The method of  claim 9 , further comprising:
 servicing an interrupt while maintaining precise architected state for a transactional block including the memory instruction and resuming execution of the transaction block after servicing the interrupt in response to the interrupt not being a transactional block failure event.   
     
     
         11 . The method of  claim 9 , further comprising: executing a subsequent update control register user-level instruction to update the control register to the unmonitored value. 
     
     
         12 . A method, comprising:
 concurrently executing a plurality of threads that share a common logical view of memory;   suspending execution of all but a first one of the threads in order to allow the first thread to execute a block of instructions atomically;   wherein said suspending is triggered by action of the first thread to invoke a hardware mechanism; and   resuming the other threads after the first thread has completed atomic execution of the block of instructions.   
     
     
         13 . The method of  claim 12 , wherein:
 said action of a first thread to invoke a hardware mechanism further comprises writing a pre-defined value to a specified memory location.   
     
     
         14 . The method of  claim 13 , wherein:
 said suspending is further triggered by an interrupt generated as a result of said action of the first thread, such that said suspending is achieved without polling, by the other threads, of the specified memory location.   
     
     
         15 . The method of  claim 12 , wherein:
 said method is performed by a multi-threaded processor that includes hardware to support transactional execution.   
     
     
         16 . The method of  claim 15 , wherein:
 said hardware includes a storage area to buffer memory writes of an atomic block.   
     
     
         17 . The method of  claim 15 , wherein:
 said hardware includes a storage area to maintain addresses of memory reads of an atomic block.   
     
     
         18 . The apparatus of  claim 1 , wherein:
 each said thread unit further comprises decode logic to receive and decode the user-level instruction.   
     
     
         19 . The apparatus of  claim 1 , wherein: the control storage area includes a control register. 
     
     
         20 . The apparatus of  claim 18 , wherein:
 said decode logic is further configured to receive and decode a status user-level instruction to read a transaction status to be held in a status register.   
     
     
         21 . The apparatus of  claim 18 , wherein:
 said decode logic is further configured to receive and decode a trap enable user-level instruction to enable traps during transactional execution.   
     
     
         22 . The apparatus of  claim 18 , wherein:
 said decode logic is further configured to receive and decode a commit user-level instruction to perform an atomic memory update.   
     
     
         23 . The apparatus of  claim 1 , further comprising: a store request buffer to hold data for the memory write instruction in response to the direct update field holding an unmonitored value to indicate writes are not to be monitored. 
     
     
         24 . The apparatus of  claim 1 , wherein said plurality of thread units further comprise:
 a plurality of processor cores.   
     
     
         25 . The apparatus of  claim 1 , wherein said plurality of thread units further comprise:
 a plurality of logical processors associated with a single processor core.   
     
     
         26 . The method of  claim 12 , wherein:
 said suspending is initiated in response to a user-level software instruction.