Inventor · disambiguated record
Xinmin Tian
Also filed as: TIAN XINMIN
38 granted patents·14 pending applications·319 citations·filing 2002–2024
97Inventor score
Top patents by PatentIndex Score
52 records- 0197US12182035B2Systems and methods for cache optimizationINTEL CORP·Filed 2020·Granted Dec 31, 2024·6 cites·21 claims
- 0297US11861761B2Graphics processing unit processing and caching improvementsINTEL CORP·Filed 2020·Granted Jan 2, 2024·8 cites·26 claims
- 0396US12124383B2Systems and methods for cache optimizationINTEL CORP·Filed 2022·Granted Oct 22, 2024·3 cites·24 claims
- 0496US12056059B2Systems and methods for cache optimizationINTEL CORP·Filed 2022·Granted Aug 6, 2024·3 cites·23 claims
- 0590US8037465B2Thread-data affinity optimization using compilerINTEL CORP·Filed 2005·Granted Oct 11, 2011·28 cites·19 claims
- 0689US7984431B2Method and apparatus for exploiting thread-level parallelismINTEL CORP·Filed 2007·Granted Jul 19, 2011·20 cites·15 claims
- 0789US7941791B2Programming environment for heterogeneous processor resource integrationWANG PERRY·Filed 2007·Granted May 10, 2011·31 cites·12 claims
- 0888US9990206B2Mechanism for instruction set based thread execution of a plurality of instruction sequencersINTEL CORP·Filed 2013·Granted Jun 5, 2018·8 cites·18 claims
- 0987US8612949B2Methods and apparatuses for compiler-creating helper threads for multi-threadingLIAO SHIH-WEI·Filed 2009·Granted Dec 17, 2013·18 cites·12 claims
- 1087US7571301B2Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processorsINTEL CORP·Filed 2006·Granted Aug 4, 2009·23 cites·27 claims
- 1186US7882498B2Method, system, and program of a compiler to parallelize source codeINTEL CORP·Filed 2006·Granted Feb 1, 2011·18 cites·24 claims
- 1285US2025103511A1Systems and methods for cache optimizationINTEL CORP·Filed 2024·Application pending·0 cites
- 1383US8793675B2Loop parallelization based on loop splitting or index arrayLIN JIN·Filed 2010·Granted Jul 29, 2014·12 cites·29 claims
- 1482US12147302B2Systems and methods for error detection and control for embedded memory and compute elementsINTEL CORP·Filed 2020·Granted Nov 19, 2024·1 cites·20 claims
- 1581US8205200B2Compiler-based scheduling optimization hints for user-level threadsLIAO SHIH-WEI·Filed 2005·Granted Jun 19, 2012·13 cites·24 claims
- 1680US12493922B2Graphics processing unit processing and caching improvementsINTEL CORP·Filed 2023·Granted Dec 9, 2025·0 cites·20 claims
- 1780US7398521B2Methods and apparatuses for thread management of multi-threadingINTEL CORP·Filed 2004·Granted Jul 8, 2008·26 cites·14 claims
- 1879US7487502B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2003·Granted Feb 3, 2009·19 cites·37 claims
- 1979US2025103430A1Systems and methods for error detection and control for embedded memory and compute elementsINTEL CORP·Filed 2024·Application pending·0 cites
- 2078US7657880B2Safe store for speculative helper threadsINTEL CORP·Filed 2003·Granted Feb 2, 2010·26 cites·30 claims
- 2176US10459858B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2017·Granted Oct 29, 2019·1 cites·14 claims
- 2275US10877910B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2017·Granted Dec 29, 2020·1 cites·10 claims
- 2373US8719819B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2005·Granted May 6, 2014·4 cites·20 claims
- 2473US7549146B2Apparatus, systems, and methods for execution-driven loop splitting and load-safe code hostingINTEL CORP·Filed 2005·Granted Jun 16, 2009·6 cites·10 claims
- 2572US7328433B2Methods and apparatus for reducing memory latency in a software applicationINTEL CORP·Filed 2003·Granted Feb 5, 2008·19 cites·34 claims
- 2668US9910796B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2013·Granted Mar 6, 2018·1 cites·9 claims
- 2765US9069605B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionINTEL CORP·Filed 2013·Granted Jun 30, 2015·1 cites·20 claims
- 2865US8589901B2Speculative region-level loop optimizationsLIN JIN·Filed 2010·Granted Nov 19, 2013·2 cites·17 claims
- 2963US9015688B2Vectorization of scalar functions including vectorization annotations and vectorized function signatures matchingTIAN XINMIN·Filed 2011·Granted Apr 21, 2015·4 cites·20 claims
- 3062US7603546B2System, method and apparatus for dependency chain processingINTEL CORP·Filed 2004·Granted Oct 13, 2009·10 cites·22 claims
- 3161US9009689B2Speculative compilation to generate advice messagesKRISHNAIYER RAKESH·Filed 2010·Granted Apr 14, 2015·3 cites·19 claims
- 3259US2017010895A1Mechanism for instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2016·Application pending·0 cites
- 3359US2021326504A1METHODS, SYSTEMS AND APPARATUS TO IMPROVE FPGA PIPELINE EMULATION EFFICIENCY ON CPUsINTEL CORP·Filed 2020·Application pending·0 cites
- 3457US10452403B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2015·Granted Oct 22, 2019·0 cites·16 claims
- 3555US10909287B2Methods, systems and apparatus to improve FPGA pipeline emulation efficiency on CPUsINTEL CORP·Filed 2017·Granted Feb 2, 2021·0 cites·21 claims
- 3655US9720697B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2012·Granted Aug 1, 2017·0 cites·18 claims
- 3753US8607235B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionHANKINS RICHARD A·Filed 2004·Granted Dec 10, 2013·3 cites·34 claims
- 3852US8868887B2Programmable event driven yield mechanism which may activate other threadsWANG HONG·Filed 2004·Granted Oct 21, 2014·1 cites·27 claims
- 3952US2023244456A1Concept for Handling Memory SpillsINTEL CORP·Filed 2023·Application pending·0 cites
- 4049US2024111826A1Hardware enhancements for double precision systolic supportINTEL CORP·Filed 2022·Application pending·0 cites
- 4146US2011067011A1Transformation of single-threaded code to speculative precomputation enabled codeWANG HONG·Filed 2010·Application pending·0 cites
- 4245US2005071438A1Methods and apparatuses for compiler-creating helper threads for multi-threadingFiled 2003·Application pending·0 cites
- 4345US2005071841A1Methods and apparatuses for thread management of mult-threadingFiled 2003·Application pending·0 cites
- 4444US2008163183A1Methods and apparatus to provide parameterized offloading on multiprocessor architecturesLI ZHIYUAN·Filed 2006·Application pending·0 cites
- 4544US2023028666A1Performing global memory atomics in a private cache of a sub-core of a graphics processing unitINTEL CORP·Filed 2021·Application pending·0 cites
- 4643US2004128489A1Transformation of single-threaded code to speculative precomputation enabled codeFiled 2002·Application pending·0 cites
- 4743US2010122073A1Handling exceptions in software transactional memory systemsNARAYANASWAMY RAVI·Filed 2008·Application pending·0 cites
- 4842US2021382717A1Hierarchical thread schedulingINTEL CORP·Filed 2020·Application pending·0 cites
- 4938US10795682B2Generating vector based selection control statementsINTEL CORP·Filed 2016·Granted Oct 6, 2020·0 cites·24 claims
- 5037US10642587B2Technologies for indirectly calling vector functionsINTEL CORP·Filed 2016·Granted May 5, 2020·0 cites·25 claims
Showing the top 50 of 52 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →