Inventor · disambiguated record
Gert Burbach
Also filed as: BURBACH GERT
13 granted patents·6 pending applications·189 citations·filing 1999–2011
92Inventor score
Top patents by PatentIndex Score
19 records- 0194US7354839B2Gate structure and a transistor having asymmetric spacer elements and methods of forming the sameADVANCED MICRO DEVICES INC·Filed 2005·Granted Apr 8, 2008·40 cites·13 claims
- 0289US7238578B2Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regionsADVANCED MICRO DEVICES INC·Filed 2005·Granted Jul 3, 2007·15 cites·18 claims
- 0386US7354836B2Technique for forming a strained transistor by a late amorphization and disposable spacersADVANCED MICRO DEVICES INC·Filed 2006·Granted Apr 8, 2008·10 cites·19 claims
- 0481US8796807B2Temperature monitoring in a semiconductor device by using a PN junction based on silicon/germanium materialsSTEPHAN ROLF·Filed 2011·Granted Aug 5, 2014·8 cites·6 claims
- 0575US6271122B1Method of compensating for material loss in a metal silicone layer in contacts of integrated circuit devicesADVANCED MICRO DEVICES INC·Filed 1999·Granted Aug 7, 2001·37 cites·19 claims
- 0674US6541863B1Semiconductor device having a reduced signal processing time and a method of fabricating the sameADVANCED MICRO DEVICES INC·Filed 2000·Granted Apr 1, 2003·20 cites·17 claims
- 0769US6720242B2Method of forming a substrate contact in a field effect transistor formed over a buried insulator layerADVANCED MICRO DEVICES INC·Filed 2001·Granted Apr 13, 2004·18 cites·15 claims
- 0867US6821840B2Semiconductor device including a field effect transistor and a passive capacitor having reduced leakage current and an improved capacitance per unit areaADVANCED MICRO DEVICES INC·Filed 2003·Granted Nov 23, 2004·13 cites·10 claims
- 0966US6943088B2Method of manufacturing a trench isolation structure for a semiconductor device with a different degree of corner roundingADVANCED MICRO DEVICES INC·Filed 2003·Granted Sep 13, 2005·14 cites·30 claims
- 1058US6656825B2Semiconductor device having an improved local interconnect structure and a method for forming such a deviceADVANCED MICRO DEVICES INC·Filed 2002·Granted Dec 2, 2003·8 cites·24 claims
- 1148US7005380B2Simultaneous formation of device and backside contacts on wafers having a buried insulator layerADVANCED MICRO DEVICES INC·Filed 2003·Granted Feb 28, 2006·3 cites·29 claims
- 1248US6905924B2Diode structure for SOI circuitsADVANCED MICRO DEVICES INC·Filed 2003·Granted Jun 14, 2005·3 cites·46 claims
- 1347US2007207583A1Method of forming a semiconductor structure comprising transistor elements with differently stressed channel regionsADVANCED MICRO DEVICES INC·Filed 2007·Application pending·0 cites
- 1446US7732291B2Semiconductor device having stressed etch stop layers of different intrinsic stress in combination with PN junctions of different design in different device regionsGLOBALFOUNDRIES INC·Filed 2006·Granted Jun 8, 2010·0 cites·9 claims
- 1543US2009218601A1Temperature monitoring in a semiconductor device by using an pn junction based on silicon/germanium materialSTEPHAN ROLF·Filed 2008·Application pending·0 cites
- 1640US2006022197A1Technique for evaluating local electrical characteristics in semiconductor devicesWIRBELEIT FRANK·Filed 2005·Application pending·0 cites
- 1737US2004217421A1SOI field effect transistor element having an ohmic substrate contactFiled 2003·Application pending·0 cites
- 1837US2005101120A1Method of forming local interconnect barrier layersFiled 2003·Application pending·0 cites
- 1936US2003203546A1SOI transistor element having an improved backside contact and method of forming the sameFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →