Inventor · disambiguated record
George P. Hoekstra
Also filed as: HOEKSTRA GEORGE · HOEKSTRA GEORGE P
37 granted patents·2 pending applications·1,246 citations·filing 1987–2015
98Inventor score
Files withFREESCALE SEMICONDUCTOR INC15MOTOROLA INC7RAMARAJU RAVINDRARAJ5INTEL CORP4HOEKSTRA GEORGE P3
Top patents by PatentIndex Score
39 records- 0198US5053990AProgram/erase selection for flash memoryINTEL CORP·Filed 1988·Granted Oct 1, 1991·354 cites·6 claims
- 0296US7443223B2Level shifting circuitFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 28, 2008·49 cites·22 claims
- 0396US5222046AProcessor controlled command port architecture for flash memoryINTEL CORP·Filed 1990·Granted Jun 22, 1993·167 cites·8 claims
- 0495US9389954B2Memory redundancy to replace addresses with multiple errorsFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Jul 12, 2016·30 cites·20 claims
- 0591US4841482ALeakage verification for flash EPROMINTEL CORP·Filed 1988·Granted Jun 20, 1989·71 cites·6 claims
- 0690US5367494ARandomly accessible memory having time overlapping memory accessesMOTOROLA INC·Filed 1993·Granted Nov 22, 1994·84 cites·11 claims
- 0789US9425829B2Adaptive error correction codes (ECCs) for electronic memoriesFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Aug 23, 2016·11 cites·17 claims
- 0888US8487657B1Dynamic logic circuitHOEKSTRA GEORGE P·Filed 2012·Granted Jul 16, 2013·10 cites·20 claims
- 0988US8400859B2Dynamic random access memory (DRAM) refreshPELLEY III PERRY H·Filed 2011·Granted Mar 19, 2013·11 cites·3 claims
- 1088US6608789B2Hysteresis reduced sense amplifier and method of operationMOTOROLA INC·Filed 2001·Granted Aug 19, 2003·49 cites·20 claims
- 1186US5751741ARate-adapted communication system and method for efficient buffer utilization thereofMOTOROLA INC·Filed 1996·Granted May 12, 1998·108 cites·18 claims
- 1285US8090913B2Coherency groups of serially coupled processing cores propagating coherency information containing write packet to memoryPELLEY III PERRY H·Filed 2010·Granted Jan 3, 2012·9 cites·5 claims
- 1385US7990795B2Dynamic random access memory (DRAM) refreshFREESCALE SEMICONDUCTOR INC·Filed 2009·Granted Aug 2, 2011·13 cites·8 claims
- 1485US4802129ARAM with dual precharge circuit and write recovery circuitryMOTOROLA INC·Filed 1987·Granted Jan 31, 1989·47 cites·7 claims
- 1583US9224439B2Memory with word line access controlRAMARAJU RAVINDRARAJ·Filed 2012·Granted Dec 29, 2015·8 cites·20 claims
- 1682US4866676ATesting arrangement for a DRAM with redundancyMOTOROLA INC·Filed 1988·Granted Sep 12, 1989·49 cites·5 claims
- 1779US9772901B2Memory reliability using error-correcting codeFREESCALE SEMICONDUCTOR INC·Filed 2015·Granted Sep 26, 2017·5 cites·20 claims
- 1879US4860261ALeakage verification for flash EPROMINTEL CORP·Filed 1989·Granted Aug 22, 1989·35 cites·1 claims
- 1978US7941637B2Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitionsFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted May 10, 2011·7 cites·7 claims
- 2075US9477548B2Error repair location cacheFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Oct 25, 2016·3 cites·16 claims
- 2175US9323602B2Error correction with extended CAMFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Apr 26, 2016·3 cites·18 claims
- 2274US7362134B2Circuit and method for latch bypassFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Apr 22, 2008·9 cites·20 claims
- 2372US8487656B1Dynamic logic circuitRAMARAJU RAVINDRARAJ·Filed 2012·Granted Jul 16, 2013·3 cites·20 claims
- 2471US9208024B2Memory ECC with hard and soft error detection and managementFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Dec 8, 2015·4 cites·20 claims
- 2570US7564738B2Double-rate memoryFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jul 21, 2009·7 cites·20 claims
- 2668US9317087B2Memory column drowsy controlRAMARAJU RAVINDRARAJ·Filed 2012·Granted Apr 19, 2016·2 cites·19 claims
- 2766US5883907AAsymmetrical digital subscriber line (ADSL) block encoder circuit and method of operationMOTOROLA INC·Filed 1997·Granted Mar 16, 1999·56 cites·40 claims
- 2866US4899317ABit line precharge in a bimos ramMOTOROLA INC·Filed 1988·Granted Feb 6, 1990·23 cites·12 claims
- 2959US9225337B2Temperature threshold circuit with hysteresisPELLEY PERRY H·Filed 2014·Granted Dec 29, 2015·1 cites·20 claims
- 3058US8402327B2Memory system with error correction and method of operationPELLEY III PERRY H·Filed 2008·Granted Mar 19, 2013·1 cites·20 claims
- 3158US7164293B2Dynamic latch having integral logic function and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jan 16, 2007·8 cites·20 claims
- 3253US9396064B2Error correction with secondary memoryHOEKSTRA GEORGE P·Filed 2014·Granted Jul 19, 2016·1 cites·20 claims
- 3351US7185170B2Data processing system having translation lookaside buffer valid bits with lock and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Feb 27, 2007·2 cites·22 claims
- 3448US2016062656A1Command Set Extension for Non-Volatile MemoryRAMARAJU RAVINDRARAJ·Filed 2014·Application pending·0 cites
- 3545US7349266B2Memory device with a data hold latchFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Mar 25, 2008·4 cites·32 claims
- 3641US6928005B2Domino comparator capable for use in a memory arrayFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Aug 9, 2005·2 cites·20 claims
- 3739US9672938B2Memory with redundancyHOEKSTRA GEORGE P·Filed 2014·Granted Jun 6, 2017·0 cites·20 claims
- 3839US9117498B2Memory with power savings for unnecessary readsRAMARAJU RAVINDRARAJ·Filed 2013·Granted Aug 25, 2015·0 cites·20 claims
- 3934US2005110522A1Multistage dynamic domino circuit with internally generated delay reset clockFiled 2003·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when George P. Hoekstra files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →