Inventor · disambiguated record
Gerrit Koch
Also filed as: KOCH GERRIT
24 granted patents·3 pending applications·51 citations·filing 2012–2020
93Inventor score
Top patents by PatentIndex Score
27 records- 0193US9274959B2Handling virtual memory address synonyms in a multi-level cache hierarchy structureGLOBALFOUNDRIES INC·Filed 2014·Granted Mar 1, 2016·23 cites·20 claims
- 0288US9934343B2System and method for generation of an integrated circuit designIBM·Filed 2016·Granted Apr 3, 2018·3 cites·11 claims
- 0384US10635555B2Verifying a graph-based coherency verification toolIBM·Filed 2018·Granted Apr 28, 2020·4 cites·20 claims
- 0483US10318406B2Determine soft error resilience while verifying architectural complianceIBM·Filed 2017·Granted Jun 11, 2019·4 cites·20 claims
- 0582US10282265B2Verifying a graph-based coherency verification toolIBM·Filed 2015·Granted May 7, 2019·4 cites·19 claims
- 0682US9245110B2Stack entry overwrite protectionIBM·Filed 2013·Granted Jan 26, 2016·7 cites·10 claims
- 0772US9959155B2Testing a data coherency algorithmIBM·Filed 2016·Granted May 1, 2018·1 cites·13 claims
- 0871US9928127B2Testing a data coherency algorithmIBM·Filed 2016·Granted Mar 27, 2018·1 cites·20 claims
- 0969US8977823B2Store buffer for transactional memoryIBM·Filed 2012·Granted Mar 10, 2015·2 cites·22 claims
- 1068US11099851B2Branch prediction for indirect branch instructionsIBM·Filed 2018·Granted Aug 24, 2021·1 cites·17 claims
- 1167US11099919B2Testing a data coherency algorithmIBM·Filed 2020·Granted Aug 24, 2021·0 cites·20 claims
- 1267US10684857B2Data prefetching that stores memory addresses in a first table and responsive to the occurrence of loads corresponding to the memory addresses stores the memory addresses in a second tableIBM·Filed 2018·Granted Jun 16, 2020·1 cites·15 claims
- 1361US10558510B2Testing a data coherency algorithmIBM·Filed 2018·Granted Feb 11, 2020·0 cites·20 claims
- 1459US10678974B2System and method for generation of an integrated circuit designIBM·Filed 2017·Granted Jun 9, 2020·0 cites·13 claims
- 1559US10572617B2System and method for generation of an integrated circuit designIBM·Filed 2017·Granted Feb 25, 2020·0 cites·10 claims
- 1657US9928321B2System and method for generation of an integrated circuit designIBM·Filed 2016·Granted Mar 27, 2018·0 cites·6 claims
- 1756US10896118B2Determine soft error resilience while verifying architectural complianceIBM·Filed 2019·Granted Jan 19, 2021·0 cites·20 claims
- 1854US9262626B2Stack entry overwrite protectionIBM·Filed 2014·Granted Feb 16, 2016·0 cites·7 claims
- 1953US9921906B2Performing a repair operation in arraysIBM·Filed 2016·Granted Mar 20, 2018·0 cites·13 claims
- 2052US10489296B2Quality of cache management in a computerIBM·Filed 2016·Granted Nov 26, 2019·0 cites·7 claims
- 2151US2018081814A1Quality of cache management in a computerIBM·Filed 2017·Application pending·0 cites
- 2250US10823782B2Ensuring completeness of interface signal checking in functional verificationIBM·Filed 2017·Granted Nov 3, 2020·0 cites·19 claims
- 2349US10830818B2Ensuring completeness of interface signal checking in functional verificationIBM·Filed 2017·Granted Nov 10, 2020·0 cites·7 claims
- 2446US2017039071A1Method for branch predictionIBM·Filed 2015·Application pending·0 cites
- 2546US2017039072A1Method for branch predictionIBM·Filed 2015·Application pending·0 cites
- 2642US9916195B2Performing a repair operation in arraysIBM·Filed 2016·Granted Mar 13, 2018·0 cites·7 claims
- 2742US9026968B2Verification assistance for digital circuit designsIBM·Filed 2014·Granted May 5, 2015·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →