Inventor · disambiguated record
Gen Pei
Also filed as: PEI GEN
9 granted patents·3 pending applications·131 citations·filing 2006–2011
89Inventor score
Top patents by PatentIndex Score
12 records- 0197US8012820B2Ultra-thin SOI CMOS with raised epitaxial source and drain and embedded SiGe PFET extensionIBM·Filed 2011·Granted Sep 6, 2011·38 cites·13 claims
- 0292US7439120B2Method for fabricating stress enhanced MOS circuitsADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 21, 2008·27 cites·15 claims
- 0391US7816767B2Negative differential resistance diode and SRAM utilizing such deviceADVANCED MICRO DEVICES INC·Filed 2009·Granted Oct 19, 2010·20 cites·18 claims
- 0491US7508050B1Negative differential resistance diode and SRAM utilizing such deviceADVANCED MICRO DEVICES INC·Filed 2006·Granted Mar 24, 2009·21 cites·14 claims
- 0584US7442601B2Stress enhanced CMOS circuits and methods for their fabricationADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 28, 2008·10 cites·18 claims
- 0680US8400854B2Identifying at-risk data in non-volatile storagePEI GEN·Filed 2010·Granted Mar 19, 2013·8 cites·31 claims
- 0768US7943999B2Stress enhanced MOS circuitsGLOBAL FOUNDRIES INC·Filed 2008·Granted May 17, 2011·3 cites·12 claims
- 0868US7416931B2Methods for fabricating a stress enhanced MOS circuitADVANCED MICRO DEVICES INC·Filed 2006·Granted Aug 26, 2008·4 cites·17 claims
- 0952US2009289305A1Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extensionIBM·Filed 2009·Application pending·0 cites
- 1048US2008217686A1Ultra-thin soi cmos with raised epitaxial source and drain and embedded sige pfet extensionIBM·Filed 2007·Application pending·0 cites
- 1147US9373548B2CMOS circuit having a tensile stress layer overlying an NMOS transistor and overlapping a portion of compressive stress layerPEI GEN·Filed 2008·Granted Jun 21, 2016·0 cites·3 claims
- 1242US2009242989A1Complementary metal-oxide-semiconductor device with embedded stressorCHAN KEVIN K·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →