Inventor · disambiguated record
Gene W. Shen
Also filed as: SHEN GENE · SHEN GENE W
27 granted patents·1 pending application·1,059 citations·filing 1994–2012
98Inventor score
Files withADVANCED MICRO DEVICES INC7HAL COMPUTER SYSTEMS INC7FUJITSU LTD4GLOBALFOUNDRIES INC3S3 INC2
Top patents by PatentIndex Score
28 records- 0191US5649136AProcessor structure and method for maintaining and restoring precise state at any instruction boundaryHAL COMPUTER SYSTEMS INC·Filed 1995·Granted Jul 15, 1997·120 cites·18 claims
- 0290US7743232B2Multiple-core processor with hierarchical microcode storeADVANCED MICRO DEVICES INC·Filed 2007·Granted Jun 22, 2010·27 cites·20 claims
- 0390US5644742AProcessor structure and method for a time-out checkpointHAL COMPUTER SYSTEMS INC·Filed 1995·Granted Jul 1, 1997·103 cites·16 claims
- 0487US7861066B2Mechanism for predicting and suppressing instruction replay in a processorADVANCED MICRO DEVICES INC·Filed 2007·Granted Dec 28, 2010·18 cites·18 claims
- 0587US5751985AProcessor structure and method for tracking instruction status to maintain precise stateHAL COMPUTER SYSTEMS INC·Filed 1995·Granted May 12, 1998·84 cites·36 claims
- 0685US7818542B2Method and apparatus for length decoding variable length instructionsGLOBALFOUNDRIES INC·Filed 2007·Granted Oct 19, 2010·15 cites·20 claims
- 0785US7685410B2Redirect recovery cache that receives branch misprediction redirects and caches instructions to be dispatched in response to the redirectsGLOBAL FOUNDRIES INC·Filed 2007·Granted Mar 23, 2010·15 cites·27 claims
- 0884US7793080B2Processing pipeline having parallel dispatch and method thereofGLOBALFOUNDRIES INC·Filed 2007·Granted Sep 7, 2010·14 cites·16 claims
- 0984US5659721AProcessor structure and method for checkpointing instructions to maintain precise stateHAL COMPUTER SYSTEMS INC·Filed 1995·Granted Aug 19, 1997·68 cites·50 claims
- 1081US5651124AProcessor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise stateHAL COMPUTER SYSTEMS INC·Filed 1995·Granted Jul 22, 1997·65 cites·24 claims
- 1178US7051300B1Method and system for architectural power estimationADVANCED MICRO DEVICES INC·Filed 2003·Granted May 23, 2006·29 cites·21 claims
- 1278US5687336AStack push/pop tracking and pairing in a pipelined processorEXPONENTIAL TECHN INC·Filed 1996·Granted Nov 11, 1997·84 cites·19 claims
- 1377US5673426AProcessor structure and method for tracking floating-point exceptionsHAL COMPUTER SYSTEMS INC·Filed 1995·Granted Sep 30, 1997·49 cites·8 claims
- 1475US5966530AStructure and method for instruction boundary machine state restorationFUJITSU LTD·Filed 1997·Granted Oct 12, 1999·43 cites·10 claims
- 1575US5675759AMethod and apparatus for register management using issue sequence prior physical register and register association validity informationFiled 1995·Granted Oct 7, 1997·79 cites·11 claims
- 1672US6553477B1Microprocessor and address translation method for microprocessorFUJITSU LTD·Filed 2000·Granted Apr 22, 2003·23 cites·31 claims
- 1770US7117290B2MicroTLB and micro tag for reducing power in a processorADVANCED MICRO DEVICES INC·Filed 2003·Granted Oct 3, 2006·17 cites·20 claims
- 1870US5655115AProcessor structure and method for watchpoint of plural simultaneous unresolved branch evaluationHAL COMPUTER SYSTEMS INC·Filed 1995·Granted Aug 5, 1997·37 cites·73 claims
- 1966US8086825B2Processing pipeline having stage-specific thread selection and method thereofSHEN GENE·Filed 2007·Granted Dec 27, 2011·3 cites·14 claims
- 2063US5790443AMixed-modulo address generation using shadow segment registersS3 INC·Filed 1996·Granted Aug 4, 1998·45 cites·19 claims
- 2163US5598550ACache controller for processing simultaneous cache accessesMOTOROLA INC·Filed 1994·Granted Jan 28, 1997·40 cites·7 claims
- 2262US7725690B2Distributed dispatch with concurrent, out-of-order dispatchADVANCED MICRO DEVICES INC·Filed 2007·Granted May 25, 2010·2 cites·18 claims
- 2359US5838940AMethod and apparatus for rotating active instructions in a parallel data processorFUJITSU LTD·Filed 1997·Granted Nov 17, 1998·38 cites·6 claims
- 2458US7818543B2Method and apparatus for length decoding and identifying boundaries of variable length instructionsGLOBALFOUNDRIES INC·Filed 2007·Granted Oct 19, 2010·1 cites·20 claims
- 2556US5790826AReduced register-dependency checking for paired-instruction dispatch in a superscalar processor with partial register writesS3 INC·Filed 1996·Granted Aug 4, 1998·32 cites·20 claims
- 2647US9176799B2Hop-by-hop error detection in a server systemADVANCED MICRO DEVICES INC·Filed 2012·Granted Nov 3, 2015·0 cites·10 claims
- 2743US2005050278A1Low power way-predicted cacheADVANCED MICRO DEVICES INC·Filed 2003·Application pending·0 cites
- 2835US5896526AProgrammable instruction trap system and methodFUJITSU LTD·Filed 1998·Granted Apr 20, 1999·8 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →