Inventor · disambiguated record
Gerard Tarroux
Also filed as: TARROUX GERARD
16 granted patents·492 citations·filing 1994–2020
94Inventor score
Top patents by PatentIndex Score
16 records- 0193US5537580AIntegrated circuit fabrication using state machine extraction from behavioral hardware description languageVLSI TECHNOLOGY INC·Filed 1994·Granted Jul 16, 1996·215 cites·27 claims
- 0292US10922469B1Methods and systems of enabling concurrent editing of hierarchical electronic circuit layoutsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Feb 16, 2021·4 cites·20 claims
- 0392US9092586B1Version management mechanism for fluid guard ring PCellsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jul 28, 2015·28 cites·19 claims
- 0489US9842183B1Methods and systems for enabling concurrent editing of electronic circuit layoutsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Dec 12, 2017·12 cites·19 claims
- 0589US8527934B2Method and system for implementing graphically editable parameterized cellsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Sep 3, 2013·15 cites·22 claims
- 0689US8347261B2Method and system for implementing graphically editable parameterized cellsCADENCE DESIGN SYSTEMS INC·Filed 2010·Granted Jan 1, 2013·16 cites·21 claims
- 0789US7555739B1Method and apparatus for maintaining synchronization between layout clonesCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 30, 2009·41 cites·33 claims
- 0885US9761204B1System and method for accelerated graphic rendering of design layout having variously sized geometric objectsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Sep 12, 2017·11 cites·20 claims
- 0985US9208273B1Methods, systems, and articles of manufacture for implementing clone design components in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Dec 8, 2015·11 cites·20 claims
- 1084US10783312B1Methods, systems, and computer program product for determining layout equivalence for a multi-fabric electronic designCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Sep 22, 2020·4 cites·20 claims
- 1184US10671793B1Editing of layout designs for fixing DRC violationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jun 2, 2020·5 cites·20 claims
- 1279US9773082B1Circuit design employing stamp patternsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Sep 26, 2017·4 cites·20 claims
- 1377US9542084B1System and method for generating vias in an electronic design by automatically using a hovering cursor indicationCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jan 10, 2017·5 cites·17 claims
- 1474US5805462AAutomatic synthesis of integrated circuits employing boolean decompositionVLSI TECHNOLOGY INC·Filed 1995·Granted Sep 8, 1998·98 cites·10 claims
- 1569US9684748B1System and method for identifying an electrical short in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jun 20, 2017·4 cites·20 claims
- 1646US6397370B1Method and system for breaking complex Boolean networksCADENCE DESIGN SYSTEMS INC·Filed 1998·Granted May 28, 2002·19 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →