Inventor · disambiguated record
Gideon N. Levinsky
Also filed as: LEVINSKY GIDEON · LEVINSKY GIDEON N
25 granted patents·4 pending applications·115 citations·filing 2004–2025
94Inventor score
Top patents by PatentIndex Score
29 records- 0196US11119767B1Atomic operation predictor to predict if an atomic operation will successfully complete and a store queue to selectively forward data based on the predictorAPPLE INC·Filed 2020·Granted Sep 14, 2021·6 cites·20 claims
- 0295US10331567B1Prefetch circuit with global quality factor to reduce aggressiveness in low power modesAPPLE INC·Filed 2017·Granted Jun 25, 2019·25 cites·18 claims
- 0393US11630789B2Scalable interruptsAPPLE INC·Filed 2021·Granted Apr 18, 2023·3 cites·20 claims
- 0492US12007920B2Scalable interruptsAPPLE INC·Filed 2023·Granted Jun 11, 2024·2 cites·20 claims
- 0591US12314200B2Scalable interruptsAPPLE INC·Filed 2024·Granted May 27, 2025·1 cites·20 claims
- 0691US12298915B1Hierarchical store queue circuitAPPLE INC·Filed 2023·Granted May 13, 2025·2 cites·20 claims
- 0785US11914511B2Decoupling atomicity from operation sizeAPPLE INC·Filed 2020·Granted Feb 27, 2024·2 cites·17 claims
- 0884US10255197B2Adaptive tablewalk translation storage buffer predictorORACLE INT CORP·Filed 2016·Granted Apr 9, 2019·6 cites·14 claims
- 0981US12229557B2Atomic operation predictor to predict whether an atomic operation will complete successfullyAPPLE INC·Filed 2024·Granted Feb 18, 2025·0 cites·20 claims
- 1081US7293221B1Methods and systems for detecting memory address transfer errors in an address busSUN MICROSYSTEMS INC·Filed 2004·Granted Nov 6, 2007·40 cites·6 claims
- 1180US8595464B2Dynamic sizing of translation lookaside buffer for power reductionLEVINSKY GIDEON N·Filed 2011·Granted Nov 26, 2013·5 cites·18 claims
- 1279US2025284649A1Scalable InterruptsAPPLE INC·Filed 2025·Application pending·0 cites
- 1378US8732438B2Anti-prefetch instructionCAPRIOLI PAUL·Filed 2008·Granted May 20, 2014·9 cites·20 claims
- 1477US11099990B2Managing serial miss requests for load operations in a non-coherent memory systemAPPLE INC·Filed 2019·Granted Aug 24, 2021·2 cites·20 claims
- 1577US2025278274A1DSB Operation with Excluded RegionAPPLE INC·Filed 2025·Application pending·0 cites
- 1675US12321746B2DSB operation with excluded regionAPPLE INC·Filed 2023·Granted Jun 3, 2025·0 cites·21 claims
- 1773US9208261B2Power reduction for fully associated translation lookaside buffer (TLB) and content addressable memory (CAM)ORACLE INT CORP·Filed 2014·Granted Dec 8, 2015·5 cites·15 claims
- 1872US2025291737A1Hierarchical Store Queue CircuitAPPLE INC·Filed 2025·Application pending·0 cites
- 1970US11928467B2Atomic operation predictor to predict whether an atomic operation will complete successfullyAPPLE INC·Filed 2021·Granted Mar 12, 2024·0 cites·20 claims
- 2067US11720360B2DSB operation with excluded regionAPPLE INC·Filed 2021·Granted Aug 8, 2023·0 cites·20 claims
- 2165US9146744B2Store queue having restricted and unrestricted entriesCAPRIOLI PAUL·Filed 2008·Granted Sep 29, 2015·3 cites·18 claims
- 2261US8065485B2Method and apparatus for determining cache storage locations based on latency requirementsLEVINSKY GIDEON N·Filed 2009·Granted Nov 22, 2011·2 cites·20 claims
- 2359US7934080B2Aggressive store merging in a processor that supports checkpointingORACLE AMERICA INC·Filed 2008·Granted Apr 26, 2011·2 cites·21 claims
- 2456US10831675B2Adaptive tablewalk translation storage buffer predictorORACLE INT CORP·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 2552US11347514B2Content-addressable memory filtering based on microarchitectural stateAPPLE INC·Filed 2019·Granted May 31, 2022·0 cites·17 claims
- 2647US11256622B2Dynamic adaptive drain for write combining bufferAPPLE INC·Filed 2020·Granted Feb 22, 2022·0 cites·20 claims
- 2745US2016055001A1Low power instruction buffer for high performance processorsORACLE INT CORP·Filed 2014·Application pending·0 cites
- 2844US10430342B2Optimizing thread selection at fetch, select, and commit stages of processor core pipelineORACLE INT CORP·Filed 2015·Granted Oct 1, 2019·0 cites·20 claims
- 2942US8601240B2Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative executionCHAUDHRY SHAILENDER·Filed 2010·Granted Dec 3, 2013·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →