Inventor · disambiguated record
Gian Sharma
Also filed as: SHARMA GIAN · SHARMA GIAN C
21 granted patents·2 pending applications·109 citations·filing 1982–2019
93Inventor score
Top patents by PatentIndex Score
23 records- 0193US10192789B1Methods of fabricating dual threshold voltage devicesSPIN TRANSFER TECH·Filed 2018·Granted Jan 29, 2019·8 cites·25 claims
- 0289US10186551B1Buried tap for a vertical transistor used with a perpendicular magnetic tunnel junction (PMTJ)SPIN TRANSFER TECH INC·Filed 2018·Granted Jan 22, 2019·6 cites·14 claims
- 0386US10192787B1Methods of fabricating contacts for cylindrical devicesSPIN TRANSFER TECH·Filed 2018·Granted Jan 29, 2019·5 cites·15 claims
- 0485US6756284B2Method for forming a sublithographic opening in a semiconductor processSILICON STORAGE TECH INC·Filed 2002·Granted Jun 29, 2004·34 cites·10 claims
- 0583US10192788B1Methods of fabricating dual threshold voltage devices with stacked gatesSPIN TRANSFER TECH·Filed 2018·Granted Jan 29, 2019·6 cites·18 claims
- 0682US10192984B1Dual threshold voltage devices with stacked gatesSPIN TRANSFER TECH·Filed 2018·Granted Jan 29, 2019·6 cites·12 claims
- 0777US10438999B2Annular vertical Si etched channel MOS devicesSPIN MEMORY INC·Filed 2017·Granted Oct 8, 2019·2 cites·8 claims
- 0875US10355047B1Fabrication methods of forming annular vertical SI etched channel MOS devicesSPIN MEMORY INC·Filed 2017·Granted Jul 16, 2019·2 cites·6 claims
- 0970US10319424B1Adjustable current selectorsSPIN MEMORY INC·Filed 2018·Granted Jun 11, 2019·2 cites·12 claims
- 1068US10460778B2Perpendicular magnetic tunnel junction memory cells having shared source contactsSPIN MEMORY INC·Filed 2017·Granted Oct 29, 2019·2 cites·9 claims
- 1168US10347822B1Fabrication methods of forming cylindrical vertical SI etched channel 3D switching devicesSPIN MEMORY INC·Filed 2017·Granted Jul 9, 2019·1 cites·14 claims
- 1267US10497415B2Dual gate memory devicesSPIN MEMORY INC·Filed 2018·Granted Dec 3, 2019·2 cites·11 claims
- 1360US10770561B2Methods of fabricating dual threshold voltage devicesSPIN MEMORY INC·Filed 2019·Granted Sep 8, 2020·0 cites·15 claims
- 1458US6969687B2Method of planarizing a semiconductor dieSILICON STORAGE TECH INC·Filed 2004·Granted Nov 29, 2005·5 cites·19 claims
- 1556US4437961AMethod for sequentially processing a multi-level interconnect circuit in a vacuum chamberNASA·Filed 1982·Granted Mar 20, 1984·22 cites·7 claims
- 1651US10854260B2Adjustable current selectorsSPIN MEMORY INC·Filed 2019·Granted Dec 1, 2020·0 cites·11 claims
- 1750US6703318B1Method of planarizing a semiconductor dieSILICON STORAGE TECH INC·Filed 2003·Granted Mar 9, 2004·2 cites·15 claims
- 1849US6699772B1Hybrid trench isolation technology for high voltage isolation using thin field oxide in a semiconductor processFiled 2002·Granted Mar 2, 2004·4 cites·20 claims
- 1948US10770510B2Dual threshold voltage devices having a first transistor and a second transistorSPIN MEMORY INC·Filed 2018·Granted Sep 8, 2020·0 cites·11 claims
- 2046US2020409272A1Fabricating Sub-Lithographic DevicesSPIN MEMORY INC·Filed 2019·Application pending·0 cites
- 2146US2020409273A1Fabricating Devices with Reduced Isolation RegionsSPIN MEMORY INC·Filed 2019·Application pending·0 cites
- 2242US10614867B2Patterning of high density small feature size pillar structuresSPIN MEMORY INC·Filed 2018·Granted Apr 7, 2020·0 cites·6 claims
- 2342US10347311B1Cylindrical vertical SI etched channel 3D switching devicesSPIN MEMORY INC·Filed 2017·Granted Jul 9, 2019·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →