Inventor · disambiguated record
Gregory J. Faanes
Also filed as: FAANES GREGORY · FAANES GREGORY J
9 granted patents·7 pending applications·415 citations·filing 1998–2020
90Inventor score
Top patents by PatentIndex Score
16 records- 0192US7437521B1Multistream processing memory-and barrier-synchronization method and apparatusCRAY INC·Filed 2003·Granted Oct 14, 2008·103 cites·11 claims
- 0291US7334110B1Decoupled scalar/vector computer architecture system and methodCRAY INC·Filed 2003·Granted Feb 19, 2008·78 cites·19 claims
- 0387US6496902B1Vector and scalar data cache for a vector multiprocessorCRAY INC·Filed 1998·Granted Dec 17, 2002·130 cites·38 claims
- 0485US8307194B1Relaxed memory consistency modelSCOTT STEVEN L·Filed 2003·Granted Nov 6, 2012·52 cites·16 claims
- 0578US6665774B2Vector and scalar data cache for a vector multiprocessorCRAY INC·Filed 2001·Granted Dec 16, 2003·25 cites·26 claims
- 0676US7519771B1System and method for processing memory instructions using a forced order queueCRAY INC·Filed 2003·Granted Apr 14, 2009·27 cites·12 claims
- 0773US11818037B2Switch device for facilitating switching in data-driven intelligent networkHEWLETT PACKARD ENTPR DEV LP·Filed 2020·Granted Nov 14, 2023·0 cites·21 claims
- 0852US2010115234A1Configurable vector length computer processorCRAY INC·Filed 2008·Application pending·0 cites
- 0948US2010318741A1Multiprocessor computer cache coherence protocolCRAY INC·Filed 2009·Application pending·0 cites
- 1047US2010115236A1Hierarchical shared semaphore registersCRAY INC·Filed 2008·Application pending·0 cites
- 1145US2010115232A1Large integer support in vector operationsJOHNSON TIMOTHY J·Filed 2008·Application pending·0 cites
- 1244US7743223B2Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor systemCRAY INC·Filed 2003·Granted Jun 22, 2010·0 cites·35 claims
- 1343US2009138680A1Vector atomic memory operationsJOHNSON TIMOTHY J·Filed 2007·Application pending·0 cites
- 1442US8601236B2Configurable vector length computer processorFAANES GREGORY J·Filed 2012·Granted Dec 3, 2013·0 cites·28 claims
- 1542US2008288756A1"or" bit matrix multiply vector instructionJOHNSON TIMOTHY J·Filed 2007·Application pending·0 cites
- 1638US2012072704A1"or" bit matrix multiply vector instructionJOHNSON TIMOTHY J·Filed 2011·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Gregory J. Faanes files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →