Configurable vector length computer processor

Abstract

A processor core, comprises one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length. Changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core.

1 . A processor core, comprising:
 one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length.   
   
   
       2 . The processor core of  claim 1 , wherein the one or more vector units is further operable to change the number of instruction streams. 
   
   
       3 . The processor core of  claim 1 , wherein the one or more vector units are operable to change the maximum vector length by changing vector register allocation in a register space. 
   
   
       4 . The processor core of  claim 1 , wherein the one or more vector units are operable to change the maximum vector length by changing instruction issue mode. 
   
   
       5 . The processor core of  claim 1 , wherein a processor comprises multiple processor cores each having one or more vector units, and the multiple processor cores are independently operable to change vector modes. 
   
   
       6 . The processor core of  claim 1 , wherein changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core. 
   
   
       7 . The processor core of  claim 1 , wherein changing vector modes comprises using the same instruction set architecture in different vector modes. 
   
   
       8 . A multiprocessor computer system, comprising:
 a plurality of processing nodes, each node comprising one or more local processor cores, wherein the one or more local processor cores each comprise one or more vector units operable to change between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length.   
   
   
       9 . The multiprocessor computer system of  claim 8 , wherein the one or more vector units is further operable to change the number of instruction streams. 
   
   
       10 . The multiprocessor computer system of  claim 8 , wherein the one or more vector units are operable to change the maximum vector length by changing vector register allocation in a register space. 
   
   
       11 . The multiprocessor computer system of  claim 8 , wherein the one or more vector units are operable to change the maximum vector length by changing instruction issue mode. 
   
   
       12 . The multiprocessor computer system of  claim 8 , wherein changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core. 
   
   
       13 . The multiprocessor computer system of  claim 8 , wherein changing vector modes comprises using the same instruction set architecture in different vector modes. 
   
   
       14 . The multiprocessor computer system of  claim 8 , wherein the one or more local processor cores are operable to independently change vector modes. 
   
   
       15 . A method of operating a vector computer processor, comprising:
 changing between a fine-grained vector mode having a shorter maximum vector length and a coarse-grained vector mode having a longer maximum vector length.   
   
   
       16 . The method of operating a vector computer processor of  claim 15 , wherein the change in vector mode is initiated by one or more of an application, an operating system, a batch system, or a processor core. 
   
   
       17 . The method of operating a vector computer processor of  claim 15 , wherein changing vector modes comprises at least one of changing the number of instruction streams, changing vector register allocation in a register space, changing instruction issue mode. 
   
   
       18 . The method of operating a vector computer processor of  claim 15 , wherein changing vector modes comprises halting all instruction stream execution in the core, flushing one or more registers in a register space, reconfiguring one or more vector registers in the register space, and restarting instruction execution in the core. 
   
   
       19 . The method of operating a vector computer processor of  claim 15 , wherein the vector computer processor comprises multiple processor cores each having one or more vector units, and the multiple processor cores are independently operable to change vector modes. 
   
   
       20 . The method of operating a vector computer processor of  claim 15 , wherein changing vector modes comprises using the same instruction set architecture in different vector modes.