Inventor · disambiguated record
Gracieli Posser
Also filed as: POSSER GRACIELI
17 granted patents·63 citations·filing 2014–2023
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
17 records- 0196US10963617B1Modifying route topology to fix clock tree violationsCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Mar 30, 2021·11 cites·20 claims
- 0295US11734485B1Routing congestion based on fractional via cost and via densityCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Aug 22, 2023·7 cites·20 claims
- 0391US10460066B1Routing framework to resolve single-entry constraint violations for integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·9 cites·20 claims
- 0490US10997352B1Routing congestion based on layer-assigned net and placement blockageCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 4, 2021·9 cites·11 claims
- 0588US10885257B1Routing congestion based on via spacing and pin densityCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 5, 2021·6 cites·14 claims
- 0684US12393760B1Wire density-aware layer assignmentCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Aug 19, 2025·1 cites·20 claims
- 0784US10460064B1Partition-aware grid graph based hierarchical global routingCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·4 cites·20 claims
- 0883US10289792B1Systems and methods for clustering pins for powerCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 14, 2019·4 cites·20 claims
- 0980US9665680B2Cell-level signal electromigrationUNIV MINNESOTA·Filed 2014·Granted May 30, 2017·7 cites·19 claims
- 1077US10685164B1Circuit design routing based on parallel run length rulesCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jun 16, 2020·2 cites·20 claims
- 1175US10460063B1Integrated circuit routing based on enhanced topologyCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·2 cites·19 claims
- 1268US10579767B1Systems and methods for routing a clock net with multiple layer rangesCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Mar 3, 2020·1 cites·15 claims
- 1359US12505274B1Detecting and modeling via during global routingCADENCE DESIGN SYSTEMS INC·Filed 2023·Granted Dec 23, 2025·0 cites·20 claims
- 1451US11461530B1Circuit design routing based on routing demand adjustmentCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 4, 2022·0 cites·19 claims
- 1550US12505277B1Cell-based pin access location generationCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Dec 23, 2025·0 cites·20 claims
- 1650US11675955B1Routing using rule-based blockage extensionCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jun 13, 2023·0 cites·20 claims
- 1746US10460065B1Routing topology generation using spine-like tree structureCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 29, 2019·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →