Inventor · disambiguated record
Guillaume Fortin
Also filed as: FORTIN GUILLAUME
22 granted patents·176 citations·filing 2005–2021
95Inventor score
Files withCADENCE DESIGN SYSTEMS INC11PMC SIERRA INC7FORTIN GUILLAUME2MICROSEMI STORAGE SOLUTIONS (U S ) INC1PMC SIERRA US INC1
Top patents by PatentIndex Score
22 records- 0195US11356304B1Quarter-rate data sampling with loop-unrolled decision feedback equalizationCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Jun 7, 2022·10 cites·20 claims
- 0294US7471107B1Active biasing in metal oxide semiconductor (MOS) differential pairsPMC SIERRA INC·Filed 2005·Granted Dec 30, 2008·31 cites·34 claims
- 0393US10547298B1Duty cycle correction system and methodCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jan 28, 2020·18 cites·19 claims
- 0492US7884660B2Variable-length digitally-controlled delay chain with interpolation-based tuningPMC SIERRA INC·Filed 2010·Granted Feb 8, 2011·11 cites·22 claims
- 0591US11323117B1Data sampling with loop-unrolled decision feedback equalizationCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted May 3, 2022·3 cites·20 claims
- 0691US7969195B1Active biasing in metal oxide semiconductor (MOS) differential pairsPMC SIERRA INC·Filed 2008·Granted Jun 28, 2011·17 cites·11 claims
- 0790US11381208B1Continuous time linear equalization system and methodCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Jul 5, 2022·3 cites·16 claims
- 0889US9831874B1Tunable impedance circuit for a transmitter output stageCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Nov 28, 2017·19 cites·20 claims
- 0988US8139702B1Clock and data recovery locking technique for large frequency offsetsFORTIN GUILLAUME·Filed 2010·Granted Mar 20, 2012·12 cites·12 claims
- 1087US10355889B1Adaptive pattern filtering for clock and data recovery to minimize interaction with decision feedback equalizationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 16, 2019·6 cites·20 claims
- 1186US11469769B1Data sampler with capacitive digital-to-analog converterCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Oct 11, 2022·2 cites·20 claims
- 1286US7738617B1Clock and data recovery locking technique for large frequency offsetsPMC SIERRA INC·Filed 2005·Granted Jun 15, 2010·17 cites·9 claims
- 1383US7733149B2Variable-length digitally-controlled delay chain with interpolation-based tuningPMC SIERRA INC·Filed 2008·Granted Jun 8, 2010·10 cites·24 claims
- 1480US9964593B1Boundary scan receiverCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted May 8, 2018·4 cites·20 claims
- 1578US11736230B1Digitally-controlled quadrature correction loopCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Aug 22, 2023·1 cites·20 claims
- 1678US8669782B1Active biasing in metal oxide semiconductor (MOS) differential pairsFORTIN GUILLAUME·Filed 2011·Granted Mar 11, 2014·4 cites·19 claims
- 1777US9252563B1Method and apparatus for driving a laser diodePMC SIERRA US INC·Filed 2013·Granted Feb 2, 2016·3 cites·5 claims
- 1864US9325305B1Active biasing in metal oxide semiconductor (MOS) differential pairsPMC SIERRA INC·Filed 2014·Granted Apr 26, 2016·1 cites·3 claims
- 1963US10225115B1Low-frequency periodic signal detectorCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Mar 5, 2019·1 cites·20 claims
- 2061US8018251B1Input/output interfacing with low powerPMC SIERRA INC·Filed 2010·Granted Sep 13, 2011·2 cites·54 claims
- 2159US9705499B1System and method for interchangeable transmission driver output stage and low-power margining modeCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Jul 11, 2017·1 cites·20 claims
- 2254US9627848B1Method and apparatus for driving a laser diodeMICROSEMI STORAGE SOLUTIONS (U S ) INC·Filed 2016·Granted Apr 18, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →