Inventor · disambiguated record
Guo-Quan Lu
Also filed as: LU GUO-QUAN
4 granted patents·7 pending applications·156 citations·filing 1996–2022
80Inventor score
Top patents by PatentIndex Score
11 records- 0190US6442033B1Low-cost 3D flip-chip packaging technology for integrated power electronics modulesVIRGINIA TECH INTELL PROP·Filed 2000·Granted Aug 27, 2002·89 cites·10 claims
- 0285US8257795B2Nanoscale metal paste for interconnect and method of useLU GUO-QUAN·Filed 2008·Granted Sep 4, 2012·25 cites·16 claims
- 0366US5855676ATube lining apparatusVIRGINIA TECH INTELL PROP·Filed 1997·Granted Jan 5, 1999·24 cites·6 claims
- 0450US2024153862A1Double-side cooled power modules with sintered-silver interposersVIRGINIA TECH INTELLECTUAL PROPERTIES INC·Filed 2022·Application pending·0 cites
- 0547US2024178126A1Double-side cooled power modulesVIRGINIA TECH INTELLECTUAL PROPERTIES INC·Filed 2022·Application pending·0 cites
- 0645US5864459AProcess for providing a glass dielectric layer on an electrically conductive substrate and electrostatic chucks made by the processVIRGINIA TECH INTELL PROP·Filed 1996·Granted Jan 26, 1999·18 cites·19 claims
- 0738US2008089839A1Preparation of Stable High Concentration Coloidal Metal Particulate SystemLU GUO-QUAN·Filed 2005·Application pending·0 cites
- 0837US2013294042A1Methods and apparatus for connecting planar power electronics devicesLU GUO-QUAN·Filed 2013·Application pending·0 cites
- 0935US2005127134A1Nano-metal composite made by deposition from colloidal suspensionsFiled 2004·Application pending·0 cites
- 1033US2007183920A1Nanoscale metal paste for interconnect and method of useLU GUO-QUAN·Filed 2005·Application pending·0 cites
- 1130US2002030276A1Dimple array interconnect technique for semiconductor deviceFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →