Inventor · disambiguated record
Gwang-Soo Kim
Also filed as: KIM GWANG-SOO
6 granted patents·7 pending applications·120 citations·filing 2004–2023
79Inventor score
Top patents by PatentIndex Score
13 records- 0190US7768775B2Display deviceSAMSUNG ELECTRONICS CO LTD·Filed 2007·Granted Aug 3, 2010·42 cites·16 claims
- 0285US7175146B2Wall mount for display apparatusSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Feb 13, 2007·76 cites·20 claims
- 0373US11444148B2Recoiled metal thin film for 3D inductor with tunable coreINTEL CORP·Filed 2018·Granted Sep 13, 2022·2 cites·14 claims
- 0458US2025112168A1Hybrid bonding with embedded alignment markersINTEL CORP·Filed 2023·Application pending·0 cites
- 0554US2025105207A1Integrated circuit packages with double hybrid bonded dies and methods of manufacturing the sameINTEL CORP·Filed 2023·Application pending·0 cites
- 0654US2025098179A1Memory layers at opposing sides of a complementary metal-oxide semiconductor layerSHARMA ABHISHEK A·Filed 2023·Application pending·0 cites
- 0753US12469801B2Moisture seal coating of hybrid bonded stacked die package assemblyINTEL CORP·Filed 2021·Granted Nov 11, 2025·0 cites·18 claims
- 0851US12431441B2Interlayer dielectric stack optimization for wafer bow reductionINTEL CORP·Filed 2021·Granted Sep 30, 2025·0 cites·17 claims
- 0951US2023207525A1Ic die stacking with mixed hybrid and solder bondingINTEL CORP·Filed 2021·Application pending·0 cites
- 1047US2024006332A1Fiducial marks for verifying alignment accuracy of bonded integrated circuit diesINTEL CORP·Filed 2022·Application pending·0 cites
- 1146US2023299123A1Inductors for hybrid bonding interconnect architecturesINTEL CORP·Filed 2022·Application pending·0 cites
- 1243US10811354B2Fuse array for integrated circuitINTEL CORP·Filed 2016·Granted Oct 20, 2020·0 cites·14 claims
- 1336US2006040713A1Display apparatusKIM GWANG-SOO·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →