Interlayer dielectric stack optimization for wafer bow reduction

Abstract

An integrated circuit (IC) die comprises a first metallization layer comprising first interconnect structures which each extend through the first metallization layer, a second metallization layer comprising second interconnect structures which each extend through the second metallization layer, an interlayer dielectric (ILD) stack between the first metallization layer and the second metallization layer. The ILD stack comprises a stress modulation layer on the first metallization layer and a capping layer on the stress modulation layer. A first intrinsic stress in a first material of the stress modulation layer is to mitigate a second intrinsic stress in the first metallization layer.

What is claimed is: 
     
       1. An integrated circuit (IC) die comprising:
 a first metallization layer comprising first interconnect structures which each extend through the first metallization layer; 
 a second metallization layer comprising second interconnect structures which each extend through the second metallization layer; 
 an interlayer dielectric (ILD) stack between the first metallization layer and the second metallization layer, the ILD stack comprising:
 a stress modulation layer on the first metallization layer, wherein a first intrinsic stress in a first material of the stress modulation layer is to mitigate a second intrinsic stress in the first metallization layer; and 
 a capping layer on the stress modulation layer, the capping layer comprising a second material; 
 
 via structures which extend through the stress modulation layer and the capping layer to couple each of the first interconnect structures to a respective one of the second interconnect structures. 
 
     
     
       2. The IC die of  claim 1 , wherein the second material in the capping layer comprises one of an oxide or a carbon-doped oxide. 
     
     
       3. The IC die of  claim 1 , wherein the second material in the capping layer has a dielectric constant of four or less. 
     
     
       4. The IC die of  claim 1 , wherein the second material in the capping layer has a thickness between ten nanometers and ten micrometers. 
     
     
       5. The IC die of  claim 1 , wherein the second material in the capping layer has an intrinsic stress of ten megapascal (MPa) or less. 
     
     
       6. The IC die of  claim 1 , wherein the first material of the stress modulation layer comprises one or more of silicon dioxide or silicon nitride. 
     
     
       7. The IC die of  claim 1 , wherein the first material of the stress modulation layer has a dielectric constant of at least five. 
     
     
       8. The IC die of  claim 1 , wherein the first material of the stress modulation layer has a thickness between ten nanometers and ten micrometers. 
     
     
       9. The IC die of  claim 1 , wherein the second material in the capping layer has an intrinsic stress of at least one hundred megapascal (MPa). 
     
     
       10. A system comprising:
 a power supply; 
 an integrated circuit (IC) die coupled to the power supply, comprising: 
 a first metallization layer comprising first interconnect structures which each extend through the first metallization layer; 
 a second metallization layer comprising second interconnect structures which each extend through the second metallization layer; 
 an interlayer dielectric (ILD) stack between the first metallization layer and the second metallization layer, the ILD stack comprising:
 a stress modulation layer on the first metallization layer, wherein a first intrinsic stress in a first material of the stress modulation layer is to mitigate a second intrinsic stress in the first metallization layer; and 
 a capping layer on the stress modulation layer, the capping layer comprising a second material; and 
 via structures which extend through the ILD stack. 
 
 
     
     
       11. The system of  claim 10 , wherein the second material in the capping layer comprises one of an oxide or a carbon-doped oxide. 
     
     
       12. The system of  claim 10 , wherein the second material in the capping layer has a dielectric constant of four or less. 
     
     
       13. The system of  claim 10 , wherein the second material in the capping layer has an intrinsic stress of ten megapascal (MPa) or less. 
     
     
       14. The system of  claim 10 , wherein the first material of the stress modulation layer comprises one or more of silicon dioxide or silicon nitride. 
     
     
       15. The system of  claim 10 , wherein the first material of the stress modulation layer has a dielectric constant of at least five. 
     
     
       16. The system of  claim 10 , wherein the first material of the stress modulation layer has a thickness between ten nanometers and ten micrometers. 
     
     
       17. The system of  claim 10 , wherein the second material in the capping layer has an intrinsic stress of at least one hundred megapascal (MPa).