Inventor · disambiguated record
Han-Shiao Chen
Also filed as: CHEN HAN-SHIAO
18 granted patents·5 pending applications·66 citations·filing 2005–2024
92Inventor score
Top patents by PatentIndex Score
23 records- 0194US10249587B1Semiconductor device including optional pad interconnectWESTERN DIGITAL TECH INC·Filed 2017·Granted Apr 2, 2019·11 cites·29 claims
- 0287US7538438B2Substrate warpage control and continuous electrical enhancementSANDISK CORP·Filed 2005·Granted May 26, 2009·15 cites·36 claims
- 0385US7746661B2Printed circuit board with coextensive electrical connectors and contact pad areasSANDISK CORP·Filed 2006·Granted Jun 29, 2010·8 cites·18 claims
- 0485US7355283B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingSANDISK CORP·Filed 2005·Granted Apr 8, 2008·10 cites·12 claims
- 0579US8878368B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingSANDISK TECHNOLOGIES INC·Filed 2013·Granted Nov 4, 2014·3 cites·16 claims
- 0674US9230919B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingSANDISK TECHNOLOGIES INC·Filed 2014·Granted Jan 5, 2016·2 cites·22 claims
- 0772US8487441B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingCHIU CHIN-TIEN·Filed 2007·Granted Jul 16, 2013·4 cites·11 claims
- 0872US7806731B2Rounded contact fingers on substrate/PCB for crack preventionSANDISK CORP·Filed 2005·Granted Oct 5, 2010·5 cites·38 claims
- 0969US8129272B2Hidden plating tracesTAKIAR HEM·Filed 2009·Granted Mar 6, 2012·3 cites·16 claims
- 1068US7967184B2Padless substrate for surface mounted componentsSANDISK CORP·Filed 2005·Granted Jun 28, 2011·4 cites·6 claims
- 1160US7592699B2Hidden plating tracesSANDISK CORP·Filed 2005·Granted Sep 22, 2009·1 cites·18 claims
- 1257US9006912B2Printed circuit board with coextensive electrical connectors and contact pad areasLIAO CHIH-CHIN·Filed 2012·Granted Apr 14, 2015·0 cites·14 claims
- 1356US10051733B2Printed circuit board with coextensive electrical connectors and contact pad areasSANDISK TECHNOLOGIES INC·Filed 2015·Granted Aug 14, 2018·0 cites·18 claims
- 1454US2025300128A1Symmetrical semiconductor dies for a semiconductor packageSANDISK TECHNOLOGIES INC·Filed 2024·Application pending·0 cites
- 1553US8217522B2Printed circuit board with coextensive electrical connectors and contact pad areasLIAO CHIH-CHIN·Filed 2010·Granted Jul 10, 2012·0 cites·13 claims
- 1653US2025293218A1Semiconductor package having an integrated passive device that acts as a spacerSANDISK TECHNOLOGIES INC·Filed 2024·Application pending·0 cites
- 1752US11031372B2Semiconductor device including dummy pull-down wire bondsWESTERN DIGITAL TECH INC·Filed 2019·Granted Jun 8, 2021·0 cites·24 claims
- 1852US9209159B2Hidden plating tracesTAKIAR HEM·Filed 2012·Granted Dec 8, 2015·0 cites·17 claims
- 1946US11139277B2Semiconductor device including contact fingers on opposed surfacesWESTERN DIGITAL TECH INC·Filed 2020·Granted Oct 5, 2021·0 cites·16 claims
- 2042US8461675B2Substrate panel with plating bar structured to allow minimum kerf widthTAKIAR HEM·Filed 2005·Granted Jun 11, 2013·0 cites·18 claims
- 2141US2007267759A1Semiconductor device with a distributed plating patternLIAO CHIH-CHIN·Filed 2006·Application pending·0 cites
- 2241US2007269929A1Method of reducing stress on a semiconductor die with a distributed plating patternLIAO CHIH-CHIN·Filed 2006·Application pending·0 cites
- 2340US2007163109A1Strip for integrated circuit packages having a maximized usable areaTAKIAR HEM·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →