Inventor · disambiguated record
Harish Kriplani
Also filed as: KRIPLANI HARISH
7 granted patents·409 citations·filing 2000–2012
88Inventor score
Technology areasG06F
Top patents by PatentIndex Score
7 records- 0196US7487475B1Systems, methods, and apparatus to perform statistical static timing analysisCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Feb 3, 2009·299 cites·23 claims
- 0285US8645881B1Methods and apparatus for performing statistical static timing analysisKRIPLANI HARISH·Filed 2012·Granted Feb 4, 2014·10 cites·12 claims
- 0382US7356451B2Assertion handling for timing model extractionCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Apr 8, 2008·30 cites·61 claims
- 0482US6928630B2Timing model extraction by timing graph reductionCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Aug 9, 2005·31 cites·53 claims
- 0578US6622290B1Timing verification method employing dynamic abstraction in core/shell partitioningCADENCE DESIGN SYSTEMS INC·Filed 2000·Granted Sep 16, 2003·34 cites·9 claims
- 0656US8448104B1Method and an apparatus to perform statistical static timing analysisKRIPLANI HARISH·Filed 2008·Granted May 21, 2013·1 cites·12 claims
- 0753US7418684B1Systems, methods, and apparatus to perform static timing analysis and optimization for multi-mode clock circuit networksCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Aug 26, 2008·4 cites·44 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →