Inventor · disambiguated record
Harsh Rawat
Also filed as: RAWAT HARSH
26 granted patents·15 pending applications·39 citations·filing 2009–2025
93Inventor score
Top patents by PatentIndex Score
41 records- 0189US11984151B2Adaptive bit line overdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted May 14, 2024·3 cites·32 claims
- 0288US12087356B2Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Sep 10, 2024·2 cites·33 claims
- 0387US12040013B2Static random access memory supporting a single clock cycle read-modify-write operationST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 16, 2024·2 cites·35 claims
- 0482US9311990B1Pseudo dual port memory using a dual port cell and a single port cell with associated valid data bits and related methodsST MICROELECTRONICS INT NV·Filed 2014·Granted Apr 12, 2016·9 cites·22 claims
- 0577US10249363B2Configurable pseudo dual port architecture for use with single port SRAMST MICROELECTRONICS INT NV·Filed 2018·Granted Apr 2, 2019·2 cites·20 claims
- 0676US2025308574A1Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 0775US10032506B2Configurable pseudo dual port architecture for use with single port SRAMST MICROELECTRONICS INT NV·Filed 2016·Granted Jul 24, 2018·2 cites·21 claims
- 0874US8144537B2Balanced sense amplifier for single ended bitline memory architectureMISHRA ANAND KUMAR·Filed 2009·Granted Mar 27, 2012·13 cites·20 claims
- 0970US9786364B1Low voltage selftime tracking circuitry for write assist based memory operationST MICROELECTRONICS INT NV·Filed 2016·Granted Oct 10, 2017·3 cites·23 claims
- 1068US2025078883A1Bit-cell architecture based in-memory computeST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1168US2025054529A1Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1267US2025174269A1Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 1366US2024395319A1Serial word line actuation with linked source voltage supply modulation for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1466US2025069678A1Built-in self test circuit for segmented static random access memory (sram) array input/outputST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 1565US12183424B2Bit-cell architecture based in-memory computeST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 31, 2024·0 cites·33 claims
- 1663US12437825B2At-speed transition fault testing for a multi-port and multi-clock memoryST MICROELECTRONICS INT NV·Filed 2023·Granted Oct 7, 2025·0 cites·40 claims
- 1762US12482518B2Enhanced accuracy of bit line reading for an in-memory compute operation by accounting for variation in read currentST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 25, 2025·0 cites·12 claims
- 1862US12469545B2Bit line read current mirroring circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2023·Granted Nov 11, 2025·0 cites·42 claims
- 1962US12170120B2Built-in self test circuit for segmented static random access memory (SRAM) array input/outputST MICROELECTRONICS INT NV·Filed 2023·Granted Dec 17, 2024·0 cites·38 claims
- 2062US12159689B2SRAM with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 3, 2024·0 cites·19 claims
- 2160US12237007B2Selective bit line clamping control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Feb 25, 2025·0 cites·39 claims
- 2259US12354644B2Adaptive word line underdrive control for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 8, 2025·0 cites·30 claims
- 2359US2025364068A1Randomized data polarity inversion of computational weight data in a digital in-memory computation processing systemST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 2459US2025372158A1Scrambled dummy column memory architecture for an in-memory computation processing systemST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 2558US2025362707A1Tiled in-memory computation processing system with randomized clock staggering and output bindingST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 2656US12353341B2Tuning of read/write cycle time delay for a memory circuit dependent on operational mode selectionST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 8, 2025·0 cites·19 claims
- 2756US12340099B2Static random access memory supporting a single clock cycle read-modify-write operation with a modulated word line assertionST MICROELECTRONICS INT NV·Filed 2023·Granted Jun 24, 2025·0 cites·21 claims
- 2856US8458545B2Method and apparatus for testing of a memory with redundancy elementsROY TANMOY·Filed 2010·Granted Jun 4, 2013·3 cites·31 claims
- 2954US12406705B2In-memory computation circuit using static random access memory (SRAM) array segmentationST MICROELECTRONICS INT NV·Filed 2023·Granted Sep 2, 2025·0 cites·24 claims
- 3051US2025054528A1Sram with fast, controlled peak current, power efficient array reset, and data corruption modes for secure applicationsST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 3148US12361982B2Memory architecture supporting both conventional memory access mode and digital in-memory computation processing modeST MICROELECTRONICS INT NV·Filed 2023·Granted Jul 15, 2025·0 cites·19 claims
- 3247US9208040B2Repair control logic for safe memories having redundant elementsST MICROELECTRONICS INT NV·Filed 2014·Granted Dec 8, 2015·0 cites·20 claims
- 3347US2024363187A1Area saving high coverage fast diagnosis memory scan designST MICROELECTRONICS INT NV·Filed 2024·Application pending·0 cites
- 3446US2024177769A1Bit line accumulation readout scheme for an analog in-memory computation processing circuitST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3545US12068026B2Low power and fast memory resetST MICROELECTRONICS INT NV·Filed 2022·Granted Aug 20, 2024·0 cites·20 claims
- 3644US9524242B2Cache memory system with simultaneous read-write in single cycleST MICROELECTRONICS INT NV·Filed 2014·Granted Dec 20, 2016·0 cites·48 claims
- 3744US2023386565A1In-memory computation circuit using static random access memory (sram) array segmentation and local compute tile read based on weighted currentST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3844US2024112728A1Analog in-memory computation processing circuit using segmented memory architectureST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 3944US2023386566A1Bit line voltage clamping read circuit for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (sram)ST MICROELECTRONICS INT NV·Filed 2023·Application pending·0 cites
- 4043US12046324B2Modular memory architecture with gated sub-array operation dependent on stored data contentST MICROELECTRONICS INT NV·Filed 2022·Granted Jul 23, 2024·0 cites·38 claims
- 4142US12176025B2Adaptive body bias management for an in-memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)ST MICROELECTRONICS INT NV·Filed 2022·Granted Dec 24, 2024·0 cites·51 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →