Inventor · disambiguated record
Haifeng Sheng
Also filed as: SHENG HAIFENG
18 granted patents·4 pending applications·51 citations·filing 2002–2020
91Inventor score
Files withGLOBALFOUNDRIES INC12GLOBALFOUNDRIES SG PTE LTD3UNIV RUTGERS2BOE HYUNDAI LCD INC1CHARTERED SEMICONDUCTOR MFG1
Top patents by PatentIndex Score
22 records- 0194US9711447B1Self-aligned lithographic patterning with variable spacingsGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 18, 2017·15 cites·20 claims
- 0293US9761452B1Devices and methods of forming SADP on SRAM and SAQP on logicGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 12, 2017·7 cites·15 claims
- 0380US10062641B2Integrated circuits including a dummy metal feature and methods of forming the sameGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Granted Aug 28, 2018·3 cites·16 claims
- 0478US9991363B1Contact etch stop layer with sacrificial polysilicon layerGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 5, 2018·2 cites·19 claims
- 0577US7400030B2Schottky diode with silver layer contacting the ZnO and MgxZn1−xO filmsUNIV RUTGERS·Filed 2005·Granted Jul 15, 2008·4 cites·24 claims
- 0674US9673301B1Methods of forming spacers on FinFET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 6, 2017·2 cites·24 claims
- 0772US7993997B2Poly profile engineering to modulate spacer induced stress for device enhancementGLOBALFOUNDRIES SG PTE LTD·Filed 2007·Granted Aug 9, 2011·3 cites·24 claims
- 0869US6846731B2Schottky diode with silver layer contacting the ZnO and MgxZn1-xO filmsUNIV RUTGERS·Filed 2002·Granted Jan 25, 2005·12 cites·20 claims
- 0961US8183149B1Method of fabricating a conductive interconnect arrangement for a semiconductor devicePERMANA DAVID M·Filed 2010·Granted May 22, 2012·2 cites·18 claims
- 1052US9147654B2Integrated circuit system employing alternating conductive layersSHENG HAIFENG·Filed 2008·Granted Sep 29, 2015·1 cites·20 claims
- 1151US2018012760A1Devices and methods of forming sadp on sram and saqp on logicGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 1246US9905472B1Silicon nitride CESL removal without gate cap height loss and resulting deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Feb 27, 2018·0 cites·19 claims
- 1345US2009315115A1Implantation for shallow trench isolation (STI) formation and for stress for transistor performance enhancementCHARTERED SEMICONDUCTOR MFG·Filed 2008·Application pending·0 cites
- 1444US8519445B2Poly profile engineering to modulate spacer induced stress for device enhancementHO VINCENT·Filed 2011·Granted Aug 27, 2013·0 cites·20 claims
- 1542US10714376B2Method of forming semiconductor material in trenches having different widths, and related structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 14, 2020·0 cites·14 claims
- 1641US12026866B2Method and apparatus for rechecking defective productBOE HYUNDAI LCD INC·Filed 2020·Granted Jul 2, 2024·0 cites·18 claims
- 1741US9966272B1Methods for nitride planarization using dielectricGLOBALFOUNDRIES INC·Filed 2017·Granted May 8, 2018·0 cites·19 claims
- 1840US9627274B1Methods of forming self-aligned contacts on FinFET devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Apr 18, 2017·0 cites·22 claims
- 1939US10056458B2Siloxane and organic-based MOL contact patterningGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 21, 2018·0 cites·19 claims
- 2038US2018350607A1Semiconductor structureGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 2136US9793208B2Plasma discharge pathGLOBALFOUNDRIES SG PTE LTD·Filed 2015·Granted Oct 17, 2017·0 cites·20 claims
- 2236US2018108732A1Notched fin structures and methods of manufactureGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →