Inventor · disambiguated record
Heemyong Park
Also filed as: PARK HEEMYONG
19 granted patents·1 pending application·708 citations·filing 1995–2004
96Inventor score
Top patents by PatentIndex Score
20 records- 0194US6492232B1Method of manufacturing vertical semiconductor deviceMOTOROLA INC·Filed 2000·Granted Dec 10, 2002·129 cites·5 claims
- 0294US6268640B1Forming steep lateral doping distribution at source/drain junctionsIBM·Filed 1999·Granted Jul 31, 2001·171 cites·29 claims
- 0392US6429084B1MOS transistors with raised sources and drainsIBM·Filed 2001·Granted Aug 6, 2002·73 cites·11 claims
- 0492US6303450B1CMOS device structures and method of making sameIBM·Filed 2000·Granted Oct 16, 2001·67 cites·15 claims
- 0587US6562666B1Integrated circuits with reduced substrate capacitanceIBM·Filed 2000·Granted May 13, 2003·41 cites·15 claims
- 0685US6509241B2Process for fabricating an MOS device having highly-localized halo regionsIBM·Filed 2000·Granted Jan 21, 2003·35 cites·19 claims
- 0783US6566198B2CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufactureIBM·Filed 2001·Granted May 20, 2003·32 cites·17 claims
- 0880US6828630B2CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufactureIBM·Filed 2003·Granted Dec 7, 2004·23 cites·19 claims
- 0976US6891228B2CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufactureIBM·Filed 2004·Granted May 10, 2005·18 cites·6 claims
- 1070US7009258B2Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous siliconIBM·Filed 2004·Granted Mar 7, 2006·11 cites·3 claims
- 1165US5872374AVertical semiconductor deviceMOTOROLA INC·Filed 1996·Granted Feb 16, 1999·22 cites·29 claims
- 1264US6808974B2CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regionsIBM·Filed 2001·Granted Oct 26, 2004·11 cites·21 claims
- 1359US6734109B2Method of building a CMOS structure on thin SOI with source/drain electrodes formed by in situ doped selective amorphous siliconIBM·Filed 2001·Granted May 11, 2004·5 cites·4 claims
- 1459US5879999AMethod of manufacturing an insulated gate semiconductor device having a spacer extensionMOTOROLA INC·Filed 1996·Granted Mar 9, 1999·19 cites·15 claims
- 1552US5780352AMethod of forming an isolation oxide for silicon-on-insulator technologyMOTOROLA INC·Filed 1995·Granted Jul 14, 1998·17 cites·18 claims
- 1649US6627511B1Reduced stress isolation for SOI devices and a method for fabricatingMOTOROLA INC·Filed 1995·Granted Sep 30, 2003·17 cites·16 claims
- 1746US6127230AVertical semiconductor device and method of manufacturing the sameMOTOROLA INC·Filed 1998·Granted Oct 3, 2000·9 cites·16 claims
- 1844US5817561AInsulated gate semiconductor device and method of manufactureMOTOROLA INC·Filed 1996·Granted Oct 6, 1998·7 cites·17 claims
- 1937US2003025167A1Activating in-situ doped gate on high dielectric constant materialsIBM·Filed 2001·Application pending·0 cites
- 2032US6097060AInsulated gate semiconductor deviceMOTOROLA INC·Filed 1998·Granted Aug 1, 2000·1 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →