Insulated gate semiconductor device

Abstract

An insulated gate semiconductor device (10) has a double spacer gate structure (45). To form the gate structure (45), a stack having sidewalls (22) is formed over a major surface (12) of a semiconductor substrate (11). A gate oxide (23) is then formed over the major surface (12) adjacent the sidewalls (22). A first polysilicon layer (24) is deposited on the gate oxide (23) and the stack. The first polysilicon layer (24) is etched to form a first conductive spacer (32) of the gate structure (45). A second polysilicon layer (44) is deposited on first spacer (32) and the stack. The second polysilicon layer (44) is then etched to form a second conductive spacer (46) of the gate structure (45). Because the double spacer gate structure (45) is formed without relying on photolithographic techniques, its size is smaller than the size of a gate structure formed using conventional photolithography.

What is claimed is: 
     
       1. An insulated gate semiconductor device comprising: a semiconductor substrate having a first conductivity type and a major surface;   a gate structure formed contiguous with the major surface, the gate structure including a first conductive spacer on a gate dielectric layer and a second conductive spacer on a first dielectric layer, wherein the first dielectric layer is thicker than the gate dielectric layer; and   a first doped region and a second doped regions formed in the semiconductor substrate and aligned to the gate structure, wherein the first and second doped regions are of a second conductivity type.   
     
     
       2. The device of claim 1, wherein the first and second conductive spacers are positioned back-to-back. 
     
     
       3. The device of claim 1, wherein the first and second conductive spacers comprise a material selected from a group consisting of polycrystalline silicon and amorphous silicon. 
     
     
       4. The device of claim 1 further comprising a third doped region of the first conductivity type formed in the semiconductor substrate below the first conductive spacer. 
     
     
       5. The device of claim 1 wherein the insulated gate semiconductor device comprises a graded-channel MOSFET device. 
     
     
       6. The device of claim 1 wherein the semiconductor substrate comprises a p-type substrate having an n-type doping layer that forms a drain extension. 
     
     
       7. A semiconductor device comprising: a substrate having a first surface and a first conductivity type;   a gate dielectric layer formed over a portion of the first surface;   a first dielectric layer formed over another portion of the first surface, wherein the first dielectric layer is thicker than the gate dielectric layer;   a first conductive spacer formed over the gate dielectric layer;   a second conductive spacer formed over the first dielectric layer, wherein the first and second conductive spacers form a gate structure;   a source region of a second conductivity type formed in the substrate adjacent one side of the gate structure; and   a drain region of the second conductivity type formed in the substrate adjacent another side of the gate structure.   
     
     
       8. The device of claim 7 further comprising a doped region of the first conductivity type formed in the substrate below a portion of the first conductive spacer. 
     
     
       9. The device of claim 7 wherein the first and second conductive spacers are positioned back-to-back. 
     
     
       10. An insulated gate semiconductor device including a gate structure formed over a semiconductor substrate, the gate structure comprising a pair of back-to-back conductive spacers, one of the pair formed over a gate dielectric layer and another of the pair formed over a first dielectric layer thicker than the gate dielectric layer, a source region formed in the semiconductor substrate aligned to one side of the gate structure, and a drain region formed in the semiconductor substrate aligned to another side of the gate structure.