Inventor · disambiguated record
Hema Ramamurthy
Also filed as: RAMAMURTHY HEMA
9 granted patents·1 pending application·60 citations·filing 1993–2021
84Inventor score
Files withRAMAMURTHY HEMA3GLOBALFOUNDRIES INC2IBM2FREESCALE SEMICONDUCTOR INC1UNIV NEW MEXICO STATE TECH TRA1
Top patents by PatentIndex Score
10 records- 0191US9799393B1Methods, apparatus and system for providing NMOS-only memory cellsGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 24, 2017·10 cites·16 claims
- 0282US8156357B2Voltage-based memory size scaling in a data processing systemZHANG SHAYAN·Filed 2009·Granted Apr 10, 2012·12 cites·20 claims
- 0367US7688656B2Integrated circuit memory having dynamically adjustable read margin and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 30, 2010·6 cites·21 claims
- 0467US5483170AIntegrated circuit fault testing implementing voltage supply rail pulsing and corresponding instantaneous current response analysisUNIV NEW MEXICO STATE TECH TRA·Filed 1993·Granted Jan 9, 1996·30 cites·16 claims
- 0556US8817562B2Devices and methods for controlling memory cell pre-charge operationsRAMAMURTHY HEMA·Filed 2012·Granted Aug 26, 2014·2 cites·18 claims
- 0652US11908519B2Pre-compare operation for compact low-leakage dual-compare cam cellIBM·Filed 2021·Granted Feb 20, 2024·0 cites·20 claims
- 0749US11837289B2Compact low-leakage multi-bit compare CAM cellIBM·Filed 2021·Granted Dec 5, 2023·0 cites·20 claims
- 0848US2018012647A1Methods, apparatus and system for providing nmos-only memory cellsGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 0935US8861301B2Clocked memory with latching predecoder circuitryRAMAMURTHY HEMA·Filed 2012·Granted Oct 14, 2014·0 cites·20 claims
- 1032US8743651B2Clocked memory with word line activation during a first portion of the clock cycleRAMAMURTHY HEMA·Filed 2012·Granted Jun 3, 2014·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →