Inventor · disambiguated record
Hideki Takeuchi
Also filed as: TAKEUCHI HIDEKI
107 granted patents·35 pending applications·2,427 citations·filing 1975–2025
99Inventor score
Top patents by PatentIndex Score
142 records- 0199US11978771B2Gate-all-around (GAA) device including a superlatticeATOMERA INC·Filed 2022·Granted May 7, 2024·7 cites·21 claims
- 0299US11848356B2Method for making semiconductor device including superlattice with oxygen and carbon monolayersATOMERA INC·Filed 2021·Granted Dec 19, 2023·6 cites·21 claims
- 0399US11837634B2Semiconductor device including superlattice with oxygen and carbon monolayersATOMERA INC·Filed 2021·Granted Dec 5, 2023·10 cites·21 claims
- 0499US11742202B2Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlatticeATOMERA INC·Filed 2022·Granted Aug 29, 2023·10 cites·23 claims
- 0599US10593761B1Method for making a semiconductor device having reduced contact resistanceATOMERA INC·Filed 2018·Granted Mar 17, 2020·51 cites·21 claims
- 0699US10580866B1Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·21 claims
- 0799US10453945B2Semiconductor device including resonant tunneling diode structure having a superlatticeATOMERA INC·Filed 2017·Granted Oct 22, 2019·45 cites·23 claims
- 0899US10249745B2Method for making a semiconductor device including a resonant tunneling diode structure having a superlatticeATOMERA INC·Filed 2017·Granted Apr 2, 2019·52 cites·22 claims
- 0999US10170604B2Method for making a semiconductor device including a resonant tunneling diode with electron mean free path control layersATOMERA INC·Filed 2017·Granted Jan 1, 2019·60 cites·20 claims
- 1099US10170603B2Semiconductor device including a resonant tunneling diode structure with electron mean free path control layersATOMERA INC·Filed 2017·Granted Jan 1, 2019·61 cites·20 claims
- 1199US9941359B2Semiconductor devices with superlattice and punch-through stop (PTS) layers at different depths and related methodsATOMERA INC·Filed 2016·Granted Apr 10, 2018·73 cites·23 claims
- 1299US9899479B2Semiconductor devices with superlattice layers providing halo implant peak confinement and related methodsATOMERA INC·Filed 2016·Granted Feb 20, 2018·89 cites·21 claims
- 1398US11923418B2Semiconductor device including a superlattice and enriched silicon 28 epitaxial layerATOMERA INC·Filed 2021·Granted Mar 5, 2024·7 cites·24 claims
- 1498US11869968B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2022·Granted Jan 9, 2024·8 cites·17 claims
- 1598US11810784B2Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layerATOMERA INC·Filed 2021·Granted Nov 7, 2023·9 cites·27 claims
- 1698US11329154B2Semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2020·Granted May 10, 2022·14 cites·18 claims
- 1798US11094818B2Method for making a semiconductor device including a superlattice and an asymmetric channel and related methodsATOMERA INC·Filed 2020·Granted Aug 17, 2021·18 cites·23 claims
- 1898US11075078B1Method for making a semiconductor device including a superlattice within a recessed etchATOMERA INC·Filed 2020·Granted Jul 27, 2021·21 cites·24 claims
- 1998US10854717B2Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Dec 1, 2020·32 cites·20 claims
- 2098US10847618B2Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 24, 2020·33 cites·20 claims
- 2198US10840337B2Method for making a FINFET having reduced contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·21 claims
- 2298US10840336B2Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methodsATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·17 claims
- 2398US10840335B2Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistanceATOMERA INC·Filed 2018·Granted Nov 17, 2020·31 cites·23 claims
- 2498US10818755B2Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistanceATOMERA INC·Filed 2018·Granted Oct 27, 2020·33 cites·21 claims
- 2598US10580867B1FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistanceATOMERA INC·Filed 2018·Granted Mar 3, 2020·49 cites·22 claims
- 2698US10410880B2Semiconductor device including a superlattice as a gettering layerATOMERA INC·Filed 2018·Granted Sep 10, 2019·45 cites·20 claims
- 2798US10381242B2Method for making a semiconductor device including a superlattice as a gettering layerATOMERA INC·Filed 2018·Granted Aug 13, 2019·45 cites·20 claims
- 2898US10367028B2CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlatticeATOMERA INC·Filed 2017·Granted Jul 30, 2019·47 cites·20 claims
- 2998US10355151B2CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalkATOMERA INC·Filed 2017·Granted Jul 16, 2019·44 cites·20 claims
- 3098US10304881B1CMOS image sensor with buried superlattice layer to reduce crosstalkATOMERA INC·Filed 2017·Granted May 28, 2019·52 cites·20 claims
- 3198US10084045B2Semiconductor device including a superlattice and replacement metal gate structure and related methodsATOMERA INC·Filed 2017·Granted Sep 25, 2018·72 cites·22 claims
- 3298US9972685B2Vertical semiconductor devices including superlattice punch through stop layer and related methodsATOMERA INC·Filed 2015·Granted May 15, 2018·64 cites·12 claims
- 3398US9406753B2Semiconductor devices including superlattice depletion layer stack and related methodsATOMERA INC·Filed 2014·Granted Aug 2, 2016·104 cites·22 claims
- 3497US11569368B2Method for making semiconductor device including a superlattice and providing reduced gate leakageATOMERA INC·Filed 2020·Granted Jan 31, 2023·8 cites·18 claims
- 3597US11469302B2Semiconductor device including a superlattice and providing reduced gate leakageATOMERA INC·Filed 2020·Granted Oct 11, 2022·10 cites·14 claims
- 3697US10615209B2CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlatticeATOMERA INC·Filed 2017·Granted Apr 7, 2020·44 cites·22 claims
- 3797US10608043B2Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlatticeATOMERA INC·Filed 2017·Granted Mar 31, 2020·47 cites·20 claims
- 3897US10608027B2Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlatticeATOMERA INC·Filed 2017·Granted Mar 31, 2020·44 cites·21 claims
- 3997US10529757B2CMOS image sensor including pixels with read circuitry having a superlatticeATOMERA INC·Filed 2017·Granted Jan 7, 2020·44 cites·17 claims
- 4097US10529768B2Method for making CMOS image sensor including pixels with read circuitry having a superlatticeATOMERA INC·Filed 2017·Granted Jan 7, 2020·44 cites·17 claims
- 4197US10461118B2Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalkATOMERA INC·Filed 2017·Granted Oct 29, 2019·44 cites·20 claims
- 4297US10396223B2Method for making CMOS image sensor with buried superlattice layer to reduce crosstalkATOMERA INC·Filed 2017·Granted Aug 27, 2019·44 cites·20 claims
- 4397US9275996B2Vertical semiconductor devices including superlattice punch through stop layer and related methodsMEARS TECHNOLOGIES INC·Filed 2014·Granted Mar 1, 2016·113 cites·10 claims
- 4497US7256107B2Damascene process for use in fabricating semiconductor structures having micro/nano gapsUNIV CALIFORNIA·Filed 2005·Granted Aug 14, 2007·41 cites·19 claims
- 4595US12046470B2Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layerATOMERA INC·Filed 2023·Granted Jul 23, 2024·1 cites·27 claims
- 4695US12014923B2Methods for making radio frequency (RF) semiconductor devices including a ground plane layer having a superlatticeATOMERA INC·Filed 2023·Granted Jun 18, 2024·1 cites·23 claims
- 4795US9722046B2Semiconductor device including a superlattice and replacement metal gate structure and related methodsATOMERA INC·Filed 2015·Granted Aug 1, 2017·13 cites·9 claims
- 4895US2025372372A1Radio frequency (rf) semiconductor devices including a ground plane layer having a superlatticeATOMERA INC·Filed 2025·Application pending·0 cites
- 4992US12020926B2Radio frequency (RF) semiconductor devices including a ground plane layer having a superlatticeATOMERA INC·Filed 2022·Granted Jun 25, 2024·1 cites·17 claims
- 5091US2025048701A1Method for making gate-all-around (gaa) device including a superlatticeATOMERA INC·Filed 2024·Application pending·0 cites
Showing the top 50 of 142 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →