US12046470B2ActiveUtilityA1

Method for making semiconductor device including a superlattice and enriched silicon 28 epitaxial layer

Assignee: ATOMERA INCPriority: Apr 21, 2021Filed: Aug 23, 2023Granted: Jul 23, 2024

Est. expiryApr 21, 2041(~14.8 yrs left)· nominal 20-yr term from priority

Inventors:Marek Hytha Keith Doran Weeks Nyles Wynn Cody Hideki Takeuchi

H10P 14/3458H10P 14/3411H10P 14/3252H10P 14/3246H10P 14/3211H10D 84/0126H10D 84/038H10D 30/60H10D 48/383H10D 64/27H10D 62/80H10D 62/83H10D 62/8162H10D 62/812H10D 30/751H10D 62/364B82Y 10/00H01L 21/8234H01L 21/02598H01L 21/02532H01L 21/02507

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Claims

Abstract

A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.

Claims

exact text as granted — not AI-modified

That which is claimed is:

1. A method for making a semiconductor device comprising:
forming a superlattice adjacent a first single crystal silicon layer having a first percentage of silicon 28, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions; and
forming a second single crystal silicon layer adjacent the superlattice on a side thereof opposite the first single crystal silicon layer, the second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28.

2. The method of claim 1 wherein the first percentage of silicon 28 is less than 93 percent.

3. The method of claim 1 wherein the second percentage of silicon 28 is greater than 95 percent.

4. The method of claim 1 wherein the second percentage of silicon 28 is greater than 99 percent.

5. The method of claim 1 further comprising forming a third single crystal silicon layer between the first single crystal silicon layer and the superlattice and having a third percentage of silicon 28 higher than the first percentage of silicon 28.

6. The method of claim 1 further comprising forming a third single crystal silicon layer between the superlattice and the second single crystal silicon layer.

7. The method of claim 1 wherein the superlattice comprises a first superlattice adjacent the first single crystal silicon layer; and further comprising:
forming a third single crystal silicon layer adjacent the first superlattice on a side thereof opposite the first single crystal silicon layer; and
forming a second superlattice adjacent the third single crystal silicon layer on a side thereof opposite the first superlattice.

8. The method of claim 1 wherein the superlattice contacts the first single crystal silicon layer, and the second single crystal silicon layer contacts the superlattice.

9. The method of claim 1 wherein the first single crystal silicon layer has a first thickness and the second single crystal silicon layer has a second thickness less than the first thickness.

10. The method of claim 1 further comprising forming at least one circuit device associated with the second single crystal silicon layer.

11. The method of claim 10 wherein the at least one circuit device comprises a plurality of quantum bit devices.

12. The method of claim 10 wherein forming the at least one circuit device comprises:
forming spaced apart source and drain regions associated with the second single crystal silicon layer defining a channel therebetween; and
forming a gate comprising a gate dielectric layer overlying the channel and a gate electrode overlying the gate dielectric layer.

13. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises oxygen.

14. A method for making a semiconductor device comprising:
forming a superlattice adjacent a first single crystal silicon layer having a first percentage of silicon 28 less than 93 percent, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions; and
forming a second single crystal silicon layer adjacent the superlattice on a side thereof opposite the first single crystal silicon layer, the second single crystal silicon layer having a second percentage of silicon 28 higher than 95 percent.

15. The method of claim 14 wherein the second percentage of silicon 28 is greater than 99 percent.

16. The method of claim 14 further comprising forming a third single crystal silicon layer between the first single crystal silicon layer and the superlattice and having a third percentage of silicon 28 higher than the first percentage of silicon 28.

17. The method of claim 14 further comprising forming a third single crystal silicon layer between the superlattice and the second single crystal silicon layer.

18. The method of claim 14 wherein the superlattice comprises a first superlattice above the first single crystal silicon layer; and further comprising:
forming a third single crystal silicon layer adjacent the first superlattice on a side thereof opposite the first single crystal silicon layer; and
forming a second superlattice adjacent the third single crystal silicon layer on a side thereof opposite the first superlattice.

19. The method of claim 14 wherein the superlattice contacts the first single crystal silicon layer, and the second single crystal silicon layer contacts the superlattice.

20. A method for making a semiconductor device comprising:
forming a superlattice adjacent a first single crystal silicon layer having a first percentage of silicon 28, the superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base silicon portions;
forming a second single crystal silicon layer adjacent the superlattice on a side thereof opposite the first single crystal silicon layer, the second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and
forming at least one circuit device associated with the second single crystal silicon layer.

21. The method of claim 20 wherein the first percentage of silicon 28 is less than 93 percent, and the second percentage of silicon 28 is greater than 95 percent.

22. The method of claim 20 further comprising forming a third single crystal silicon layer between the first single crystal silicon layer and the superlattice and having a third percentage of silicon 28 higher than the first percentage of silicon 28.

23. The method of claim 20 further comprising forming a third single crystal silicon layer between the superlattice and the second single crystal silicon layer.

24. The method of claim 20 wherein the superlattice comprises a first superlattice above the first single crystal silicon layer; and further comprising:
forming a third single crystal silicon layer adjacent the first superlattice on a side thereof opposite the first single crystal silicon layer; and
forming a second superlattice adjacent the third single crystal silicon layer on a side thereof opposite the first superlattice.

25. The method of claim 20 wherein the superlattice contacts the first single crystal silicon layer, and the second single crystal silicon layer contacts the superlattice.

26. The method of claim 20 wherein the at least one circuit device comprises a plurality of quantum bit devices.

27. The method of claim 20 wherein forming the at least one circuit device comprises:
forming spaced apart source and drain regions associated with the second single crystal silicon layer defining a channel therebetween; and
forming a gate comprising a gate dielectric layer overlying the channel and a gate electrode overlying the gate dielectric layer.

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