Inventor · disambiguated record
Howard G. Sachs
Also filed as: SACHS HOWARD · SACHS HOWARD G · SACHS HOWARD GEORGE
20 granted patents·12 pending applications·1,112 citations·filing 1976–2007
97Inventor score
Files withINTERGRAPH CORP15TELAIRITY SEMICONDUCTOR INC14INSTRUMENTATION SPECIALTIES CO1SACHS HOWARD1TELERATY SYSTEMS INC1
Top patents by PatentIndex Score
32 records- 0194US5091846ACache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherencyINTERGRAPH CORP·Filed 1989·Granted Feb 25, 1992·170 cites·20 claims
- 0289US5560028ASoftware scheduled superscalar computer architectureINTERGRAPH CORP·Filed 1995·Granted Sep 24, 1996·172 cites·23 claims
- 0389US4933835AApparatus for maintaining consistency of a cache memory with a primary memoryINTERGRAPH CORP·Filed 1989·Granted Jun 12, 1990·119 cites·23 claims
- 0488US4860192AQuadword boundary cache systemINTERGRAPH CORP·Filed 1986·Granted Aug 22, 1989·112 cites·33 claims
- 0585US5255384AMemory address translation system having modifiable and non-modifiable translation mechanismsINTERGRAPH CORP·Filed 1991·Granted Oct 19, 1993·114 cites·22 claims
- 0683US4115779AAutomobile trunk antenna mountINSTRUMENTATION SPECIALTIES CO·Filed 1976·Granted Sep 19, 1978·56 cites·14 claims
- 0782US4899275ACache-MMU systemINTERGRAPH CORP·Filed 1989·Granted Feb 6, 1990·78 cites·54 claims
- 0878US4884197AMethod and apparatus for addressing a cache memoryINTERGRAPH CORP·Filed 1986·Granted Nov 28, 1989·62 cites·16 claims
- 0975US6910199B2Circuit group design methodologiesTELAIRITY SEMICONDUCTOR INC·Filed 2001·Granted Jun 21, 2005·20 cites·19 claims
- 1073US6892293B2VLIW processor and method thereforINTERGRAPH CORP·Filed 1998·Granted May 10, 2005·55 cites·90 claims
- 1170US7103736B2System for repair of ROM programming errors or defectsTELAIRITY SEMICONDUCTOR INC·Filed 2003·Granted Sep 5, 2006·15 cites·18 claims
- 1264US6360313B1Instruction cache associative crossbar switchINTERGRAPH CORP·Filed 2000·Granted Mar 19, 2002·11 cites·122 claims
- 1364US5794003AInstruction cache associative crossbar switch systemINTERGRAPH CORP·Filed 1996·Granted Aug 11, 1998·34 cites·33 claims
- 1460US7058832B2Idle power reduction for state machinesTELAIRITY SEMICONDUCTOR INC·Filed 2002·Granted Jun 6, 2006·8 cites·12 claims
- 1559US7039791B2Instruction cache association crossbar switchINTERGRAPH CORP·Filed 2002·Granted May 2, 2006·5 cites·27 claims
- 1658US7234123B2Circuit group design methodologiesTELAIRITY SEMICONDUCTOR INC·Filed 2004·Granted Jun 19, 2007·5 cites·13 claims
- 1757US5502829AApparatus for obtaining data from a translation memory based on carry signal from adderINTERGRAPH CORP·Filed 1993·Granted Mar 26, 1996·29 cites·21 claims
- 1856US2008038384A1Formulation to aid in management of Irritable Bowel Syndrome with urgency symptoms.SACHS HOWARD·Filed 2007·Application pending·0 cites
- 1953US2008059758A1Memory architecture for vector processorTELAIRITY SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2053US2008059760A1Instructions for Vector ProcessorTELAIRITY SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2153US2008059759A1Vector Processor ArchitectureTELAIRITY SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2253US2008059757A1Convolver Architecture for Vector ProcessorTELAIRITY SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2353US2008052489A1Multi-Pipe Vector Block Matching OperationsTELAIRITY SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2451US2007150697A1Vector processor with multi-pipe vector block matchingTELAIRITY SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2548US5463750AMethod and apparatus for translating virtual addresses in a data processing system having multiple instruction pipelines and separate TLB'sINTERGRAPH CORP·Filed 1993·Granted Oct 31, 1995·19 cites·14 claims
- 2647US5996062AMethod and apparatus for controlling an instruction pipeline in a data processing systemINTERGRAPH CORP·Filed 1996·Granted Nov 30, 1999·17 cites·25 claims
- 2742US2008186316A1Minimized Table LookupTELAIRITY SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2841US6282635B1Method and apparatus for controlling an instruction pipeline in a data processing systemINTERGRAPH CORP·Filed 1999·Granted Aug 28, 2001·11 cites·29 claims
- 2939US2006259657A1Direct memory access (DMA) method and apparatus and DMA for video processingTELAIRITY SEMICONDUCTOR INC·Filed 2005·Application pending·0 cites
- 3038US2006259737A1Vector processor with special purpose registers and high speed memory accessTELAIRITY SEMICONDUCTOR INC·Filed 2005·Application pending·0 cites
- 3138US2003140218A1General purpose state machineTELERATY SYSTEMS INC·Filed 2002·Application pending·0 cites
- 3237US2006259807A1Method and apparatus for clock synchronization between a processor and external devicesTELAIRITY SEMICONDUCTOR INC·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →