Inventor · disambiguated record
Hsing-Jen Wann
Also filed as: WANN HSING-JEN · WANN HSING-JEN C
23 granted patents·1 pending application·1,989 citations·filing 1993–2007
97Inventor score
Top patents by PatentIndex Score
24 records- 0198US5489792ASilicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibilityUNIV CALIFORNIA·Filed 1994·Granted Feb 6, 1996·369 cites·13 claims
- 0298US5448513ACapacitorless DRAM device on silicon-on-insulator substrateUNIV CALIFORNIA·Filed 1993·Granted Sep 5, 1995·361 cites·10 claims
- 0397US6300649B1Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibilityUNIV CALIFORNIA·Filed 2000·Granted Oct 9, 2001·154 cites·9 claims
- 0497US6121077ASilicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibilityUNIV CALIFORNIA·Filed 1999·Granted Sep 19, 2000·167 cites·4 claims
- 0597US5780899ADelta doped and counter doped dynamic threshold voltage MOSFET for ultra-low voltage operationUNIV CALIFORNIA·Filed 1995·Granted Jul 14, 1998·197 cites·4 claims
- 0696US5982003ASilicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibilityUNIV CALIFORNIA·Filed 1995·Granted Nov 9, 1999·162 cites·2 claims
- 0794US7056794B2FET gate structure with metal gate electrode and silicide contactIBM·Filed 2004·Granted Jun 6, 2006·96 cites·20 claims
- 0894US6268640B1Forming steep lateral doping distribution at source/drain junctionsIBM·Filed 1999·Granted Jul 31, 2001·171 cites·29 claims
- 0988US6936522B2Selective silicon-on-insulator isolation structure and methodIBM·Filed 2003·Granted Aug 30, 2005·37 cites·22 claims
- 1088US6429091B1Patterned buried insulatorIBM·Filed 2000·Granted Aug 6, 2002·55 cites·8 claims
- 1184US6297127B1Self-aligned deep trench isolation to shallow trench isolationIBM·Filed 2000·Granted Oct 2, 2001·40 cites·9 claims
- 1282US7326983B2Selective silicon-on-insulator isolation structure and methodIBM·Filed 2005·Granted Feb 5, 2008·8 cites·14 claims
- 1377US5599728AMethod of fabricating a self-aligned high speed MOSFET deviceUNIV CALIFORNIA·Filed 1994·Granted Feb 4, 1997·41 cites·4 claims
- 1469US7923786B2Selective silicon-on-insulator isolation structure and methodIBM·Filed 2007·Granted Apr 12, 2011·3 cites·17 claims
- 1564US6025242AFabrication of semiconductor device having shallow junctions including an insulating spacer by thermal oxidation creating taper-shaped isolationIBM·Filed 1999·Granted Feb 15, 2000·22 cites·20 claims
- 1663US6974736B2Method of forming FET silicide gate structures incorporating inner spacersIBM·Filed 2004·Granted Dec 13, 2005·10 cites·20 claims
- 1762US5998273AFabrication of semiconductor device having shallow junctionsIBM·Filed 1999·Granted Dec 7, 1999·25 cites·16 claims
- 1860US7081393B2Reduced dielectric constant spacer materials integration for high speed logic gatesIBM·Filed 2004·Granted Jul 25, 2006·8 cites·20 claims
- 1955US5998248AFabrication of semiconductor device having shallow junctions with tapered spacer in isolation regionIBM·Filed 1999·Granted Dec 7, 1999·19 cites·18 claims
- 2052US6057724AMethod and apparatus for synchronized clock distributionIBM·Filed 1998·Granted May 2, 2000·24 cites·9 claims
- 2149US6022771AFabrication of semiconductor device having shallow junctions and sidewall spacers creating taper-shaped isolation where the source and drain regions meet the gate regionsIBM·Filed 1999·Granted Feb 8, 2000·14 cites·19 claims
- 2242US6653686B2Structure and method of controlling short-channel effect of very short channel MOSFETIBM·Filed 1998·Granted Nov 25, 2003·6 cites·20 claims
- 2338US2004033665A1Structure and method of controlling short-channel effect of very short channel MOSFETFiled 2003·Application pending·0 cites
- 2434US6975133B1Logic circuits having linear and cellular gate transistorsIBM·Filed 2004·Granted Dec 13, 2005·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →