Structure and method of controlling short-channel effect of very short channel MOSFET

Abstract

A semiconductor device comprising a gate having an approximately 0.05 μm channel length, an oxide layer below the gate, a self-aligned compensation implant below the oxide layer, a halo implant surrounding the self-aligned compensation implant below the oxide layer; and gate and drain regions on opposite sides of the halo implant and below the oxide layer.

I claim:  
     
         1 . A semiconductor device comprising: 
 a gate; and    a compensation implant below said gate.    
     
     
         2 . The semiconductor device as in  claim 1 , wherein said semiconductor device has an approximately 0.05 μm channel length.  
     
     
         3 . The semiconductor device as in  claim 1 , wherein said compensation implant reduces a threshold voltage of said semiconductor device.  
     
     
         4 . The semiconductor device as in  claim 1 , wherein said compensation implant has a doping concentration for controlling a threshold voltage reduction of said semiconductor device.  
     
     
         5 . The semiconductor device as in  claim 4 , wherein said doping concentration varies depending upon a channel length of said semiconductor device.  
     
     
         6 . The semiconductor device as in  claim 1 , wherein said compensation implant is self-aligned with said gate.  
     
     
         7 . The semiconductor device as in  claim 1 , further comprising: 
 a halo implant surrounding said compensation implant; and    gate and drain regions on opposite sides of said halo implant.    
     
     
         8 . A semiconductor device comprising: 
 a gate;    an oxide layer below said gate;    a self-aligned compensation implant below said oxide layer;    a halo implant surrounding said self-aligned compensation implant below said oxide layer; and    gate and drain regions on opposite sides of said halo implant and below said oxide layer.    
     
     
         9 . The semiconductor device as in  claim 8 , wherein said self-aligned compensation implant reduces a threshold voltage of said semiconductor device.  
     
     
         10 . The semiconductor device as in  claim 8 , wherein said self-aligned compensation implant has a doping concentration for controlling a threshold voltage reduction of said semiconductor device that varies depending upon a channel length of said semiconductor device.  
     
     
         11 . A method of manufacturing a semiconductor device comprising steps of: 
 forming a channel above a substrate;    implanting an impurity in said substrate through said channel to form a compensation implant in said semiconductor substrate; and    forming a gate above said compensation implant.    
     
     
         12 . The method as in  claim 11 , further comprising steps of: 
 prior to said step of forming said channel, successively depositing an oxide layer and a dielectric layer on said substrate, said step of forming said channel comprising a step of forming said channel in said oxide layer and said dielectric layer;    prior to said step of forming said gate, depositing an oxide layer in said channel on said substrate;    after said step of forming said gate, removing all of said dielectric layer and a portion of said oxide layer such that said oxide layer remains between said gate and said semiconductor substrate; and    doping areas of said semiconductor substrate adjacent said gate to form a halo implant and source and drain regions.    
     
     
         13 . The method as in  claim 11 , further comprising a step, prior to said implanting step, of forming spacers in said channel.  
     
     
         14 . The method as in  claim 11 , wherein said implanting step aligns said compensation implant and said gate.  
     
     
         15 . The method as in  claim 11 , wherein said implanting step further comprises a step of varying a doping concentration of said compensation implant for controlling a threshold voltage reduction of said semiconductor device.  
     
     
         16 . The method as in  claim 15 , wherein said step of varying a doping concentration of said compensation implant is dependent upon a channel length of said semiconductor device.  
     
     
         17 . A method of manufacturing a semiconductor device comprising steps of: 
 successively depositing an oxide layer and a dielectric layer on a semiconductor substrate;    forming a channel in said oxide layer and said dielectric layer;    forming spacers in said channel;    implanting an impurity in said semiconductor substrate through said channel to form a self-aligned compensation implant in said semiconductor substrate;    depositing an oxide layer in said channel on said semiconductor substrate;    filling said channel with a conductive material to form a gate over said oxide layer;    removing all of said dielectric layer;    removing a portion of said oxide layer such that said oxide layer remains between said gate and said semiconductor substrate; and    doping areas of said semiconductor substrate adjacent said gate to form a halo implant and source and drain regions in said semiconductor substrate.    
     
     
         18 . The method as in  claim 17 , wherein said implanting step further comprises a step of varying a doping concentration of said self-aligned compensation implant for controlling a threshold voltage reduction of said semiconductor device.  
     
     
         19 . The method as in  claim 17 , wherein said step of varying a doping concentration of said self-aligned compensation implant is dependent upon a channel length of said semiconductor device.  
     
     
         20 . A method of manufacturing a semiconductor device comprising steps of: 
 successively depositing an oxide layer and a dielectric layer on a semiconductor substrate;    forming a channel in said oxide layer and said dielectric layer;    depositing an oxide layer in said channel on said semiconductor substrate;    partially filling said channel with a conductive material;    implanting an impurity in said semiconductor substrate through said conductive material and said oxide layer in said channel to form a self-aligned compensation implant in said semiconductor substrate;    completely filling said channel with said conductive material to form a gate over said oxide layer;    removing all of said dielectric layer;    removing a portion of said oxide layer such that said oxide layer remains between said gate and said semiconductor substrate; and    doping areas of said semiconductor substrate adjacent said gate to form a halo implant and source and drain regions in said semiconductor substrate.    
     
     
         21 . The method as in  claim 20 , wherein said implanting step further comprises a step of varying a doping concentration of said self-aligned compensation implant for controlling a threshold voltage reduction of said semiconductor device.  
     
     
         22 . The method as in  claim 20 , wherein said step of varying a doping concentration of said self-aligned compensation implant is dependent upon a channel length of said semiconductor device.  
     
     
         23 . A method of manufacturing a semiconductor device comprising steps of: 
 forming a sacrificial mask over a gate area of a substrate;    forming spacers adjacent said sacrificial mask;    forming an opening in said sacrificial mask;    implanting an impurity in said semiconductor substrate through said opening in said sacrificial mask to form a self-aligned compensation implant in said semiconductor substrate;    removing said sacrificial mask;    depositing an oxide layer between said spacers on said semiconductor substrate;    forming a gate between said spacers and over said oxide layer; and    doping areas of said semiconductor substrate adjacent said gate to form a halo implant and source and drain regions in said semiconductor substrate.    
     
     
         24 . The method as in  claim 23 , wherein said implanting step further comprises a step of varying a doping concentration of said self-aligned compensation implant for controlling a threshold voltage reduction of said semiconductor device.  
     
     
         25 . The method as in  claim 23 , wherein said step of varying a doping concentration of said self-aligned compensation implant is dependent upon a channel length of said semiconductor device.