Inventor · disambiguated record
Huan-Chih Tsai
Also filed as: TSAI HUAN-CHIH
11 granted patents·4 pending applications·320 citations·filing 1998–2020
92Inventor score
Top patents by PatentIndex Score
15 records- 0194US9621613B1Bitrate adaptation transitioning using key framesVISUALON INC·Filed 2014·Granted Apr 11, 2017·31 cites·16 claims
- 0294US7739629B2Method and mechanism for implementing electronic designs having power information specifications backgroundCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jun 15, 2010·42 cites·29 claims
- 0393US11259069B1Synchronized video playerVISUALON INC·Filed 2020·Granted Feb 22, 2022·11 cites·18 claims
- 0489US8516422B1Method and mechanism for implementing electronic designs having power information specifications backgroundWANG QI·Filed 2010·Granted Aug 20, 2013·13 cites·31 claims
- 0585US6694466B1Method and system for improving the test quality for scan-based BIST using a general test application schemeAGERE SYSTEMS INC·Filed 1999·Granted Feb 17, 2004·62 cites·19 claims
- 0682US7694251B2Method and system for verifying power specifications of a low power designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Apr 6, 2010·16 cites·24 claims
- 0782US7669165B2Method and system for equivalence checking of a low power designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Feb 23, 2010·16 cites·20 claims
- 0881US11172246B1Bitrate adaptation for low latency streamingVISUALON INC·Filed 2020·Granted Nov 9, 2021·3 cites·21 claims
- 0980USRE44479EMethod and mechanism for implementing electronic designs having power information specifications backgroundWANG QI·Filed 2012·Granted Sep 3, 2013·5 cites·29 claims
- 1079US6463561B1Almost full-scan BIST method and system having higher fault coverage and shorter test application timeAGERE SYST GUARDIAN CORP·Filed 1999·Granted Oct 8, 2002·46 cites·2 claims
- 1173US6256759B1Hybrid algorithm for test point selection for scan-based BISTAGERE SYSTEMS INC·Filed 1998·Granted Jul 3, 2001·75 cites·19 claims
- 1246US2010305933A1Method and Apparatus for Verifying Logic Circuits Using Vector Emulation with Vector SubstitutionCHANG CHIOUMIN M·Filed 2009·Application pending·0 cites
- 1345US2010100860A1Method and apparatus for debugging an electronic system design (esd) prototypeCHANG CHIOUMIN M·Filed 2008·Application pending·0 cites
- 1437US2012005547A1Scalable system debugger for prototype debuggingCHANG CHIOUMIN M·Filed 2010·Application pending·0 cites
- 1533US2011289469A1Virtual interconnection method and apparatusHUANG THOMAS B·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →