Inventor · disambiguated record
Hwa-Joon Oh
Also filed as: OH HWA-JOON
19 granted patents·6 pending applications·164 citations·filing 1995–2008
94Inventor score
Top patents by PatentIndex Score
25 records- 0186US8229989B2Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point unitsDHONG SANG HOO·Filed 2008·Granted Jul 24, 2012·14 cites·4 claims
- 0276US6914453B2Integrated logic and latch design with clock gating at static input signalsIBM·Filed 2003·Granted Jul 5, 2005·18 cites·23 claims
- 0374US7058830B2Power saving in a floating point unit using a multiplier and aligner bypassIBM·Filed 2003·Granted Jun 6, 2006·21 cites·20 claims
- 0474US6829682B2Destructive read architecture for dynamic random access memoriesIBM·Filed 2001·Granted Dec 7, 2004·19 cites·44 claims
- 0571US7137021B2Power saving in FPU with gated power based on opcodes and dataIBM·Filed 2003·Granted Nov 14, 2006·19 cites·12 claims
- 0667US7290023B2High performance implementation of exponent adjustment in a floating point designIBM·Filed 2003·Granted Oct 30, 2007·13 cites·13 claims
- 0766US8131795B2High speed adder design for a multiply-add based floating point unitDHONG SANG HOO·Filed 2008·Granted Mar 6, 2012·3 cites·11 claims
- 0860US7392270B2Apparatus and method for reducing the latency of sum-addressed shiftersIBM·Filed 2004·Granted Jun 24, 2008·7 cites·10 claims
- 0958US7490119B2High speed adder design for a multiply-add based floating point unitIBM·Filed 2003·Granted Feb 10, 2009·5 cites·21 claims
- 1058US7245159B2Protecting one-hot logic against short-circuits during power-onIBM·Filed 2004·Granted Jul 17, 2007·7 cites·21 claims
- 1157US8166085B2Reducing the latency of sum-addressed shiftersDHONG SANG HOO·Filed 2008·Granted Apr 24, 2012·1 cites·16 claims
- 1256US6510093B1Method and apparatus for cycle time reduction in a memory system using alternating reference cells and isolated sense linesIBM·Filed 2001·Granted Jan 21, 2003·9 cites·19 claims
- 1355US7447725B2Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point unitsIBM·Filed 2004·Granted Nov 4, 2008·3 cites·1 claims
- 1455US7149877B2Byte execution unit for carrying out byte instructions in a processorIBM·Filed 2003·Granted Dec 12, 2006·4 cites·11 claims
- 1553US2008263336A1Processor Having Efficient Function Estimate InstructionsIBM·Filed 2008·Application pending·0 cites
- 1648US7406589B2Processor having efficient function estimate instructionsIBM·Filed 2005·Granted Jul 29, 2008·0 cites·7 claims
- 1748US6587388B2Method and apparatus for reducing write operation time in dynamic random access memoriesIBM·Filed 2001·Granted Jul 1, 2003·5 cites·32 claims
- 1848US2007061553A1Byte Execution Unit for Carrying Out Byte Instructions in a ProcessorDHONG SANG H·Filed 2006·Application pending·0 cites
- 1947US7237163B2Leakage current reduction system and methodIBM·Filed 2004·Granted Jun 26, 2007·3 cites·19 claims
- 2046US5689621AModular feedforward neural network architecture with learningUNIV MICHIGAN STATE·Filed 1995·Granted Nov 18, 1997·13 cites·11 claims
- 2146US2006053190A1Construction of a folded leading zero anticipatorSONY COMPUTER ENTERTAINMENT INC·Filed 2004·Application pending·0 cites
- 2246US2006101108A1Using a leading-sign anticipator circuit for detecting sticky-bit informationSONY COMPUTER ENTERTAINMENT INC·Filed 2004·Application pending·0 cites
- 2346US2006031272A1Alignment shifter supporting multiple precisionsIBM·Filed 2004·Application pending·0 cites
- 2443US7469265B2Methods and apparatus for performing multi-value range checksIBM·Filed 2003·Granted Dec 23, 2008·0 cites·24 claims
- 2543US2005228844A1Fast operand formatting for a high performance multiply-add floating point-unitIBM·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →