Byte Execution Unit for Carrying Out Byte Instructions in a Processor

Abstract

A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.

1 . A byte execution unit, comprising: 
 logic coupled to receive byte instruction information, to receive a first operand from a first source register, to receive a second operand from a second source register, and configured to perform an operation specified by the byte instruction information upon at least one of the first operand or the second operand, thereby producing a result in a destination register, wherein the byte instruction information specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operations,    wherein responsive to a count ones in bytes operation, the byte execution unit counts a number of logical one bits in each byte of at least the first operand and stores each result in a corresponding byte of the destination register;    wherein responsive to an average bytes operation, the byte execution unit averages each byte of the first operand with a corresponding byte of the second operand and stores each result in a corresponding byte of the destination register;    wherein responsive to an absolute differences of bytes operation, the byte execution unit subtracts each byte of the first operand from a corresponding byte of the second operand to form an intermediate result, determines an absolute value of each intermediate result to form a final result, and stores each final result in a corresponding byte of the destination register; and    wherein responsive to a sum bytes into halfwords operation, the byte execution unit sums a number of corresponding one-byte portions of the first operand or the second operand and stores each result in a corresponding halfword of the destination register.    
   
   
       2 . The byte execution unit as recited in  claim 1 , wherein each the first operand and the second operand comprises a plurality of bits, and wherein the bits of each of the first operand and the second operand are grouped to form a plurality of corresponding 8-bit bytes.  
   
   
       3 . The byte execution unit as recited in  claim 2 , wherein each of the first operand and the second operand comprises 128 bits, and wherein the bits of each of the first operand and the second operand are grouped to form 16 corresponding bytes.  
   
   
       4 - 7 . (canceled)  
   
   
       8 . A byte execution unit, comprising: 
 pre-processing logic coupled to receive a plurality of operands and configured to perform an operation upon the operands dependent upon an operation specified by a byte instruction, thereby producing an intermediate result;    adder logic coupled to receive the intermediate result and configured to perform an addition operation upon the intermediate result, thereby producing a sum and a sum+ 1 ;    post-processing logic coupled to receive the sum and sum+ 1  and configured to perform an operation upon the sum and sum+ 1  dependent upon the operation specified by a byte instruction, thereby producing a result; and    a control unit coupled to the pre-processing logic, the adder logic, and the post-processing logic wherein responsive to the byte instruction, the control unit sets control signals to configure the pre-processing logic, the adder logic, and the post-processing logic to perform either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation.    
   
   
       9 . (canceled)  
   
   
       10 . (canceled)  
   
   
       11 . The byte execution unit as recited in  claim 8 , wherein the pre-processing logic comprises population counter logic coupled to receive the operands and configured to produce population output signals indicative of numbers of logic ones in portions of the operands.  
   
   
       12 . The byte execution unit as recited in  claim 8 , wherein the pre-processing logic comprises compressor logic coupled to receive the operands and configured to perform a compression function.  
   
   
       13 . The byte execution unit as recited in  claim 8 , wherein the post-processing logic comprises end-around carry logic configured to perform an end-around carry function.  
   
   
       14 . The byte execution unit as recited in  claim 8 , wherein the post-processing logic is configured to perform bit shift operations.  
   
   
       15 - 28 . (canceled)  
   
   
       29 . A data processing system, comprising: 
 a memory system comprising a byte instruction, wherein the byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation; and    a processor coupled to the memory system and configured to fetch and execute instructions from the memory system, wherein the processor comprises: 
 a byte execution unit coupled to receive byte instruction information, to receive a first operand from a first source register, and to receive a second operand from a second source register, and configured to perform an operation specified by the byte instruction information upon at least one of the first operand or the second operand, thereby producing a result in a destination register,  
 wherein responsive to a count ones in bytes operation, the byte execution unit counts a number of logical one bits in each byte of at least the first operand and stores each result in a corresponding byte of the destination register;  
 wherein responsive to an average bytes operation, the byte execution unit averages each byte of the first operand with a corresponding byte of the second operand and stores each result in a corresponding byte of the destination register;  
 wherein responsive to an absolute differences of bytes operation, the byte execution unit subtracts each byte of the first operand from a corresponding byte of the second operand to form an intermediate result determines an absolute value of each intermediate result to form a final result, and stores each final result in a corresponding byte of the destination register; and  
 wherein responsive to a sum bytes into halfwords operation, the byte execution unit sums a number of corresponding one-byte portions of the first operand or the second operand and stores each result in a corresponding halfword of the destination register.  
   
   
   
       30 . The data processing system as recited in  claim 29 , wherein each of the first operand and the second operand comprises a plurality of bits, and wherein the bits of each of the first operand and the second operand are grouped to form a plurality of corresponding 8-bit bytes.  
   
   
       31 . The data processing system as recited in  claim 30 , wherein each of the first operand and the second operand comprises 128 bits, and wherein the bits of each of the first operand and the second operand are grouped to form 16 corresponding bytes.  
   
   
       32 . The bye execution unit of  claim 8 , wherein responsive to a count ones in bytes operation, the control unit sets control signals to configure the pre-processing logic, the adder logic, and the post-processing logic to count a number of logical one bits in each byte of at least the first operand and to store each result in a corresponding byte of the destination register.  
   
   
       33 . The bye execution unit of  claim 8 , wherein responsive to an average bytes operation, the control unit sets control signals to configure the pre-processing logic, the adder logic, and the post-processing logic to average each byte of the first operand with a corresponding byte of the second operand and to store each result in a corresponding byte of the destination register.  
   
   
       34 . The bye execution unit of  claim 8 , wherein responsive to an absolute differences of bytes operation, the control unit sets control signals to configure the pre-processing logic, the adder logic, and the post-processing logic to subtract each byte of the first operand from a corresponding byte of the second operand to form an intermediate result, to determine an absolute value of each intermediate result to form a final result, and to store each final result in a corresponding byte of the destination register.  
   
   
       35 . The bye execution unit of  claim 8 , wherein responsive to a sum bytes into halfwords operation, the control unit sets control signals to configure the pre-processing logic, the adder logic, and the post-processing logic to sum a number of corresponding one-byte portions of the first operand or the second operand and to store each result in a corresponding halfword of the destination register.  
   
   
       36 . The byte execution unit of  claim 8 , wherein each of the operands comprises a plurality of bits, and wherein the bits of each of the operands are grouped to form a plurality of corresponding 8-bit bytes.  
   
   
       37 . The byte execution unit of  claim 36 , wherein each of the operands comprises 128 bits, and wherein the bits of each of the operands are grouped to form 16 corresponding bytes.