Inventor · disambiguated record
Brad W. Michael
Also filed as: MICHAEL BRAD W · MICHAEL BRAD WILLIAM
41 granted patents·8 pending applications·288 citations·filing 1992–2021
97Inventor score
Top patents by PatentIndex Score
49 records- 0195US8520740B2Arithmetic decoding accelerationFLACHS BRIAN·Filed 2010·Granted Aug 27, 2013·56 cites·21 claims
- 0292US8522225B2Rewriting branch instructions using branch stubsCHEN TONG·Filed 2010·Granted Aug 27, 2013·18 cites·20 claims
- 0391US10169013B2Arranging binary code based on call graph partitioningIBM·Filed 2017·Granted Jan 1, 2019·5 cites·21 claims
- 0491US9430418B2Synchronization and order detection in a memory systemIBM·Filed 2013·Granted Aug 30, 2016·11 cites·17 claims
- 0587US9594647B2Synchronization and order detection in a memory systemIBM·Filed 2016·Granted Mar 14, 2017·4 cites·1 claims
- 0684US8782381B2Dynamically rewriting branch instructions in response to cache line evictionCHEN TONG·Filed 2012·Granted Jul 15, 2014·7 cites·19 claims
- 0784US8631225B2Dynamically rewriting branch instructions to directly target an instruction cache locationCHEN TONG·Filed 2010·Granted Jan 14, 2014·7 cites·15 claims
- 0883US8713548B2Rewriting branch instructions using branch stubsCHEN TONG·Filed 2012·Granted Apr 29, 2014·6 cites·13 claims
- 0981US8627051B2Dynamically rewriting branch instructions to directly target an instruction cache locationCHEN TONG·Filed 2012·Granted Jan 7, 2014·5 cites·10 claims
- 1081US8516230B2SPE software instruction cacheCHEN TONG·Filed 2009·Granted Aug 20, 2013·10 cites·19 claims
- 1180US10297335B2Tracking address ranges for computer memory errorsIBM·Filed 2016·Granted May 21, 2019·4 cites·17 claims
- 1280US7203608B1Impedane measurement of chip, package, and board power supply system using pseudo impulse responseIBM·Filed 2006·Granted Apr 10, 2007·10 cites·20 claims
- 1379US7486096B2Method and apparatus for testing to determine minimum operating voltages in electronic devicesIBM·Filed 2006·Granted Feb 3, 2009·9 cites·20 claims
- 1478US11372703B1Reduced system memory latency via a variable latency interfaceIBM·Filed 2021·Granted Jun 28, 2022·1 cites·19 claims
- 1578US10304560B2Performing error correction in computer memoryIBM·Filed 2016·Granted May 28, 2019·2 cites·14 claims
- 1677US10353669B2Managing entries in a mark table of computer memory errorsIBM·Filed 2016·Granted Jul 16, 2019·2 cites·14 claims
- 1777US10338999B2Confirming memory marks indicating an error in computer memoryIBM·Filed 2016·Granted Jul 2, 2019·2 cites·20 claims
- 1877US9459851B2Arranging binary code based on call graph partitioningCHEN TONG·Filed 2010·Granted Oct 4, 2016·3 cites·14 claims
- 1975US9916144B2Arranging binary code based on call graph partitioningIBM·Filed 2016·Granted Mar 13, 2018·1 cites·19 claims
- 2075US6421053B1Block rendering method for a graphics subsystemIBM·Filed 1999·Granted Jul 16, 2002·59 cites·19 claims
- 2174US7610531B2Modifying a test pattern to control power supply noiseIBM·Filed 2006·Granted Oct 27, 2009·7 cites·21 claims
- 2269US9940204B2Memory error recoveryIBM·Filed 2015·Granted Apr 10, 2018·1 cites·17 claims
- 2368US9600253B2Arranging binary code based on call graph partitioningCHEN TONG·Filed 2012·Granted Mar 21, 2017·1 cites·7 claims
- 2461US11017875B2Tracking address ranges for computer memory errorsIBM·Filed 2019·Granted May 25, 2021·0 cites·18 claims
- 2561US10971246B2Performing error correction in computer memoryIBM·Filed 2019·Granted Apr 6, 2021·0 cites·18 claims
- 2661US10901839B2Common high and low random bit error correction logicIBM·Filed 2018·Granted Jan 26, 2021·1 cites·20 claims
- 2761US10324694B2Arranging binary code based on call graph partitioningIBM·Filed 2017·Granted Jun 18, 2019·0 cites·20 claims
- 2860US7870309B2Multithreaded programmable direct memory access engineIBM·Filed 2008·Granted Jan 11, 2011·1 cites·21 claims
- 2959US7870308B2Programmable direct memory access engineIBM·Filed 2008·Granted Jan 11, 2011·1 cites·21 claims
- 3059US5430847AMethod and system for extending system buses to external devicesIBM·Filed 1992·Granted Jul 4, 1995·44 cites·1 claims
- 3156US9495254B2Synchronization and order detection in a memory systemIBM·Filed 2016·Granted Nov 15, 2016·0 cites·1 claims
- 3255US10140186B2Memory error recoveryIBM·Filed 2017·Granted Nov 27, 2018·0 cites·1 claims
- 3355US7149877B2Byte execution unit for carrying out byte instructions in a processorIBM·Filed 2003·Granted Dec 12, 2006·4 cites·11 claims
- 3454US12118236B2Dynamically allocating memory controller resources for extended prefetchingIBM·Filed 2021·Granted Oct 15, 2024·0 cites·19 claims
- 3554US7986330B2Method and apparatus for generating gammacorrected antialiased linesIBM·Filed 2001·Granted Jul 26, 2011·5 cites·23 claims
- 3653US2008263336A1Processor Having Efficient Function Estimate InstructionsIBM·Filed 2008·Application pending·0 cites
- 3752US8145804B2Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processorFLACHS BRIAN KING·Filed 2009·Granted Mar 27, 2012·1 cites·19 claims
- 3851US8918553B2Multithreaded programmable direct memory access engineFLACHS BRIAN K·Filed 2012·Granted Dec 23, 2014·0 cites·17 claims
- 3949US8230136B2Multithreaded programmable direct memory access engineFLACHS BRIAN K·Filed 2010·Granted Jul 24, 2012·0 cites·21 claims
- 4048US10824504B2Common high and low random bit error correction logicIBM·Filed 2018·Granted Nov 3, 2020·0 cites·20 claims
- 4148US7406589B2Processor having efficient function estimate instructionsIBM·Filed 2005·Granted Jul 29, 2008·0 cites·7 claims
- 4248US2007061553A1Byte Execution Unit for Carrying Out Byte Instructions in a ProcessorDHONG SANG H·Filed 2006·Application pending·0 cites
- 4347US8677101B2Method and apparatus for cooperative software multitasking in a processor system with a partitioned register fileFLACHS BRIAN·Filed 2007·Granted Mar 18, 2014·0 cites·15 claims
- 4447US2011320786A1Dynamically Rewriting Branch Instructions in Response to Cache Line EvictionCHEN TONG·Filed 2010·Application pending·0 cites
- 4542US2007186135A1Processor system and methodology with background error handling featureFLACHS BRIAN·Filed 2006·Application pending·0 cites
- 4640US2006224869A1Combination of forwarding/bypass network with history fileFLACHS BRIAN K·Filed 2005·Application pending·0 cites
- 4740US2006179277A1System and method for instruction line buffer holding a branch target bufferFLACHS BRIAN K·Filed 2005·Application pending·0 cites
- 4838US2008092006A1Optimizing a Set of LBIST Patterns to Enhance Delay Fault CoverageDAKWALA NIKHIL·Filed 2006·Application pending·0 cites
- 4937US2009070654A1Design Structure For A Processor System With Background Error Handling FeatureIBM·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →