Inventor · disambiguated record
Hyeok-Sang Oh
Also filed as: OH HYEOK SANG
17 granted patents·3 pending applications·118 citations·filing 2004–2021
92Inventor score
Top patents by PatentIndex Score
20 records- 0194US10461027B2Semiconductor device including via plug and method of forming the sameSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Oct 29, 2019·10 cites·20 claims
- 0294US7176126B2Method of fabricating dual damascene interconnectionSAMSUNG ELECTRONICS CO LTD·Filed 2005·Granted Feb 13, 2007·39 cites·18 claims
- 0392US10475739B2Semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Nov 12, 2019·8 cites·20 claims
- 0490US8232200B1Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed therebyOH HYEOK-SANG·Filed 2011·Granted Jul 31, 2012·21 cites·20 claims
- 0586US10276505B2Integrated circuit device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Apr 30, 2019·5 cites·20 claims
- 0684US10229876B2Wiring structures and semiconductor devicesKIM JUN JUNG·Filed 2016·Granted Mar 12, 2019·9 cites·20 claims
- 0779US10497649B2Integrated circuit device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Dec 3, 2019·2 cites·15 claims
- 0874US10535600B2Semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Jan 14, 2020·2 cites·19 claims
- 0972US10847454B2Semiconductor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Nov 24, 2020·1 cites·20 claims
- 1070US10510658B2Semiconductor devicesSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Dec 17, 2019·1 cites·20 claims
- 1170US7163890B2Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layerSAMSUNG ELECTRONICS CO LTD·Filed 2004·Granted Jan 16, 2007·15 cites·15 claims
- 1269US11600569B2Integrated circuit device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2021·Granted Mar 7, 2023·0 cites·20 claims
- 1364US8026166B2Interconnect structures comprising capping layers with low dielectric constants and methods of making the sameIBM·Filed 2008·Granted Sep 27, 2011·3 cites·7 claims
- 1461US8373273B2Methods of forming integrated circuit devices having damascene interconnects therein with metal diffusion barrier layers and devices formed therebySAMSUNG ELECTRONICS CO LTD·Filed 2012·Granted Feb 12, 2013·1 cites·5 claims
- 1560US11049810B2Integrated circuit device and method of manufacturing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Jun 29, 2021·0 cites·20 claims
- 1658US7534720B2Methods of fabricating semiconductor device having slope at lower sides of interconnection hole with etch-stop layerSAMSUNG ELECTRONICS CO LTD·Filed 2006·Granted May 19, 2009·1 cites·10 claims
- 1753US2019304903A1Semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2019·Application pending·0 cites
- 1846US2006049439A1Image device and method of fabricating the sameSAMSUNG ELECTRONICS CO LTD·Filed 2005·Application pending·0 cites
- 1943US10916437B2Methods of forming micropatterns and substrate processing apparatusSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Feb 9, 2021·0 cites·19 claims
- 2035US2006024941A1Method of forming metal interconnect of semiconductor deviceSAMSUNG ELECTRONICS CO LTD·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →