Method of fabricating dual damascene interconnection

Abstract

In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.

1. A method of fabricating a dual damascene interconnection, comprising:
 (a) forming a lower interconnect feature on a substrate; 
 (b) forming a dielectric layer on the lower interconnect feature; 
 (c) forming a hard mask on the dielectric layer, wherein the hard mask is formed using BN, and the dielectric layer is formed using an oxide layer; 
 (d) forming a via in the dielectric layer using the hard mask as an etch mask; 
 (e) forming a trench hard mask defining a trench by patterning the hard mask; 
 (f) forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask; 
 (g) removing the trench hard mask using wet etch; and 
 (h) forming an upper interconnection line by filling the trench and the via with an interconnection material. 
 
   
   
     2. The method of  claim 1 , wherein the hard mask is formed to a thickness of 1000 Å or greater. 
   
   
     3. The method of  claim 1 , wherein operation (g) comprises performing wet etch at an etch selectivity of the trench hard mask relative to the dielectric layer equal to or greater than 2000:1. 
   
   
     4. The method of  claim 3 , wherein the wet etch is performed using a phosphoric acid solution. 
   
   
     5. The method of  claim 3 , further comprising:
 forming an etch stop layer on the lower interconnect feature before operation (b), wherein operation (d) comprises forming the via exposing the etch stop layer in the dielectric layer using the hard mask as the etch mask; and 
 exposing the lower interconnection feature by removing the etch stop layer exposed through the via before operation (h). 
 
   
   
     6. The method of  claim 3 , further comprising forming an etch stop layer on the lower interconnection feature before operation (b),
 wherein operation (d) comprises forming the via exposing the etch stop layer in the dielectric layer using the hard mask as the etch mask, and 
 operation (g) comprises exposing the lower interconnect feature by simultaneously removing the etch stop layer exposed through the via and the trench hard mask using a single wet etching process. 
 
   
   
     7. The method of  claim 6 , wherein the etch stop layer and the trench hard mask are formed using a same material. 
   
   
     8. The method of  claim 1 , wherein operation (c) comprises forming a hard mask layer on the dielectric layer, forming a photoresist pattern defining the via on the hard mask layer, and patterning the hard mask using the photoresist pattern as an etch mask; and
 operation (d) comprises forming the via by dry etching the dielectric layer using the photoresist pattern and the hard mask as the etch mask. 
 
   
   
     9. The method of  claim 1 , wherein operation (e) comprises forming the trench hard mask using a photoresist pattern defining the trench, and removing the photoresist pattern; and
 operation (f) comprises forming the trench by dry etching the dielectric layer using the trench hard mask as the etch mask at an etch selectivity of the dielectric layer relative to the trench hard mask equal to or greater than 30:1. 
 
   
   
     10. The method of  claim 9 , wherein the dry etch is performed using one of CxFy and CxHyFz as a major etching gas. 
   
   
     11. The method of  claim 1 , wherein the upper interconnection line is a copper interconnection line. 
   
   
     12. The method of  claim 11 , wherein the dielectric layer is formed using one of FSG and SiOC. 
   
   
     13. A method of fabricating a dual damascene interconnection, comprising:
 (a) forming a lower interconnect feature on a substrate; 
 (b) forming an etch stop layer on the lower interconnect feature; 
 (c) forming a dielectric layer on the etch stop layer 
 (d) forming a BN hard mask on the dielectric layer; 
 (e) forming a via exposing the etch stop layer in the dielectric layer using the BN hard mask as an etch mask; 
 (f) forming a trench hard mask defining a trench by patterning the BN hard mask; 
 (g) forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask; 
 (h) removing the trench hard mask by performing wet etch using a phosphoric acid solution; 
 (i) exposing the lower interconnect feature by removing the etch stop layer exposed through the via; and 
 (j) forming an upper interconnection line by filling the trench and the via with an interconnection material. 
 
   
   
     14. The method of  claim 13 , wherein operation (d) comprises forming a BN hard mask layer on the dielectric layer, forming a photoresist pattern defining the via on the BN hard mask layer, and patterning the BN hard mask using the photoresist pattern as an etch mask; and
 operation (e) comprises forming the via exposing the etch stop layer by dry etching the dielectric layer using the photoresist pattern and the BN hard mask as the etch mask. 
 
   
   
     15. The method of  claim 14 , wherein operation (f) comprises forming the trench hard mask using a photoresist pattern defining the trench, and removing the photoresist pattern; and
 operation (g) comprises forming the trench by dry etching the dielectric layer using the trench hard mask as the etch mask at an etch selectivity of the dielectric layer relative to the trench hard mask equal to or greater than 30:1. 
 
   
   
     16. The method of  claim 15 , wherein the dry etch is performed using one of CxFy and CxHyFz as a major etching gas. 
   
   
     17. The method of  claim 15 , wherein the upper interconnection line is a copper interconnection line. 
   
   
     18. The method of  claim 17 , wherein the dielectric layer is formed using one of FSG and SiOC.