Inventor · disambiguated record
Iulian C. Gradinariu
Also filed as: GRADINARIU IULIAN · GRADINARIU IULIAN C · GRADINARIU IULIAN CONSTANTIN
30 granted patents·1 pending application·329 citations·filing 1997–2023
97Inventor score
Files withCYPRESS SEMICONDUCTOR CORP23Longitude Flash Memory Solutions Ltd4GRADINARIU IULIAN CONSTANTIN1PORTER EDSON WAYNE1RAGHAVAN VIJAY KUMAR SRINIVASA1
Top patents by PatentIndex Score
31 records- 0198US7504876B1Substrate bias feedback scheme to reduce chip leakage powerCYPRESS SEMICONDUCTOR CORP·Filed 2006·Granted Mar 17, 2009·47 cites·19 claims
- 0296US9449655B1Low standby power with fast turn on for non-volatile memory devicesCYPRESS SEMICONDUCTOR CORP·Filed 2015·Granted Sep 20, 2016·20 cites·20 claims
- 0390US7262586B1Shunt type voltage regulatorCYPRESS SEMICONDUCTOR CORP·Filed 2005·Granted Aug 28, 2007·20 cites·20 claims
- 0488US7746160B1Substrate bias feedback scheme to reduce chip leakage powerCYPRESS SEMICONDUCTOR CORP·Filed 2009·Granted Jun 29, 2010·11 cites·18 claims
- 0587US8791683B1Voltage-mode band-gap reference circuit with temperature drift and output voltage trimsPORTER EDSON WAYNE·Filed 2011·Granted Jul 29, 2014·11 cites·19 claims
- 0687US7683701B2Low power Bandgap reference circuit with increased accuracy and reduced area consumptionCYPRESS SEMICONDUCTOR CORP·Filed 2005·Granted Mar 23, 2010·17 cites·15 claims
- 0785US9639226B2Differential sigma-delta capacitance sensing devices and methodsCYPRESS SEMICONDUCTOR CORP·Filed 2015·Granted May 2, 2017·4 cites·20 claims
- 0885US8283972B1Substrate bias feedback scheme to reduce chip leakage powerRAGHAVAN VIJAY KUMAR SRINIVASA·Filed 2011·Granted Oct 9, 2012·5 cites·21 claims
- 0982US6323701B1Scheme for reducing leakage current in an input bufferCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Nov 27, 2001·41 cites·36 claims
- 1081US8587365B1Substrate bias feedback scheme to reduce chip leakage powerCYPRESS SEMICONDUCTOR CORP·Filed 2012·Granted Nov 19, 2013·4 cites·19 claims
- 1181US6163495AArchitecture, method(s) and circuitry for low power memoriesCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Dec 19, 2000·38 cites·20 claims
- 1279US9438240B1Biasing circuit for level shifter with isolationCYPRESS SEMICONDUCTOR CORP·Filed 2015·Granted Sep 6, 2016·5 cites·20 claims
- 1377US12014800B2Low standby power with fast turn on method for non-volatile memory devicesLongitude Flash Memory Solutions Ltd·Filed 2023·Granted Jun 18, 2024·0 cites·20 claims
- 1475US8085085B1Substrate bias feedback scheme to reduce chip leakage powerSRINIVASA RAGHAVAN VIJAY KUMAR·Filed 2010·Granted Dec 27, 2011·4 cites·19 claims
- 1571US5828614AMemory cell sensing method and circuitry for bit line equalizationCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Oct 27, 1998·30 cites·14 claims
- 1670US11581029B2Low standby power with fast turn on method for non-volatile memory devicesLongitude Flash Memory Solutions Ltd·Filed 2021·Granted Feb 14, 2023·0 cites·16 claims
- 1765US6378008B1Output data path scheme in a memory deviceCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Apr 23, 2002·23 cites·18 claims
- 1864US6662315B1Parallel test in asynchronous memory with single-ended output pathCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Dec 9, 2003·11 cites·20 claims
- 1957US10998019B2Low standby power with fast turn on method for non-volatile memory devicesLongitude Flash Memory Solutions Ltd·Filed 2019·Granted May 4, 2021·0 cites·14 claims
- 2054US6118727ASemiconductor memory with interdigitated array having bit line pairs accessible from either of two sides of the arrayCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Sep 12, 2000·14 cites·12 claims
- 2153US10510387B2Low standby power with fast turn on method for non-volatile memory devicesLongitude Flash Memory Solutions Ltd·Filed 2018·Granted Dec 17, 2019·0 cites·8 claims
- 2250US11990907B2Closed loop oscillatorCYPRESS SEMICONDUCTOR CORP·Filed 2022·Granted May 21, 2024·0 cites·16 claims
- 2350US10062423B2Low standby power with fast turn on for non-volatile memory devicesCYPRESS SEMICONDUCTOR CORP·Filed 2016·Granted Aug 28, 2018·0 cites·5 claims
- 2449US10254812B1Low inrush circuit for power up and deep power down exitCYPRESS SEMICONDUCTOR CORP·Filed 2018·Granted Apr 9, 2019·0 cites·19 claims
- 2549US6535437B1Block redundancy in ultra low power memory circuitsCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted Mar 18, 2003·5 cites·23 claims
- 2648US6493283B1Architecture, method (s) and circuitry for low power memoriesCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Dec 10, 2002·4 cites·20 claims
- 2743US9866216B1Biasing circuit for level shifter with isolationCYPRESS SEMICONDUCTOR CORP·Filed 2016·Granted Jan 9, 2018·0 cites·20 claims
- 2842US6629185B1Architecture, circuitry and method of transferring data into and/or out of an interdigitated memory arrayCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Sep 30, 2003·8 cites·16 claims
- 2940US6530040B1Parallel test in asynchronous memory with single-ended output pathCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Mar 4, 2003·6 cites·4 claims
- 3038US6674682B2Architecture, method(s) and circuitry for low power memoriesCYPRESS SEMICONDUCTOR CORP·Filed 2002·Granted Jan 6, 2004·1 cites·20 claims
- 3134US2012206284A1Interpolating digital-to-analog converter with separate bias current source for each differential input transistor pairGRADINARIU IULIAN CONSTANTIN·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →