Inventor · disambiguated record
James Y. Cho
Also filed as: CHO JAMES B · CHO JAMES Y · CHO JAMES YOUNGSAE
25 granted patents·2 pending applications·1,827 citations·filing 1986–2023
97Inventor score
Top patents by PatentIndex Score
27 records- 0199US6877076B1Memory controller with programmable configurationBROADCOM CORP·Filed 2003·Granted Apr 5, 2005·287 cites·8 claims
- 0298US6766389B2System on a chip for networkingBROADCOM CORP·Filed 2001·Granted Jul 20, 2004·180 cites·19 claims
- 0397US7991922B2System on a chip for networkingBROADCOM CORP·Filed 2009·Granted Aug 2, 2011·59 cites·18 claims
- 0497US6625685B1Memory controller with programmable configurationBROADCOM CORP·Filed 2000·Granted Sep 23, 2003·192 cites·78 claims
- 0596US6526483B1Page open hint in transactionsBROADCOM CORP·Filed 2000·Granted Feb 25, 2003·179 cites·24 claims
- 0694US5091846ACache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherencyINTERGRAPH CORP·Filed 1989·Granted Feb 25, 1992·170 cites·20 claims
- 0793US7418534B2System on a chip for networkingBROADCOM CORP·Filed 2004·Granted Aug 26, 2008·64 cites·19 claims
- 0889US4933835AApparatus for maintaining consistency of a cache memory with a primary memoryINTERGRAPH CORP·Filed 1989·Granted Jun 12, 1990·119 cites·23 claims
- 0988US4860192AQuadword boundary cache systemINTERGRAPH CORP·Filed 1986·Granted Aug 22, 1989·112 cites·33 claims
- 1086US6681302B2Page open hint in transactionsBROADCOM CORP·Filed 2002·Granted Jan 20, 2004·42 cites·21 claims
- 1185US5255384AMemory address translation system having modifiable and non-modifiable translation mechanismsINTERGRAPH CORP·Filed 1991·Granted Oct 19, 1993·114 cites·22 claims
- 1284US7660931B2System on a chip for networkingBROADCOM CORP·Filed 2008·Granted Feb 9, 2010·9 cites·12 claims
- 1384US6449701B1Out of order associative queue in two clock domainsBROADCOM CORP·Filed 2000·Granted Sep 10, 2002·34 cites·31 claims
- 1482US4899275ACache-MMU systemINTERGRAPH CORP·Filed 1989·Granted Feb 6, 1990·78 cites·54 claims
- 1578US6816932B2Bus precharge during a phase of a clock signal to eliminate idle clock cycleBROADCOM CORP·Filed 2001·Granted Nov 9, 2004·23 cites·21 claims
- 1678US4884197AMethod and apparatus for addressing a cache memoryINTERGRAPH CORP·Filed 1986·Granted Nov 28, 1989·62 cites·16 claims
- 1776US6633938B1Independent reset of arbiters and agents to allow for delayed agent resetBROADCOM CORP·Filed 2000·Granted Oct 14, 2003·20 cites·24 claims
- 1869US6629218B2Out of order associative queue in two clock domainsBROADCOM CORP·Filed 2002·Granted Sep 30, 2003·12 cites·34 claims
- 1967US6678767B1Bus sampling on one edge of a clock signal and driving on another edgeBROADCOM CORP·Filed 2000·Granted Jan 13, 2004·10 cites·35 claims
- 2062US7093052B2Bus sampling on one edge of a clock signal and driving on another edgeBROADCOM CORP·Filed 2003·Granted Aug 15, 2006·7 cites·11 claims
- 2161US12360769B2Branch target buffer operation with auxiliary indirect cacheAKEANA INC·Filed 2023·Granted Jul 15, 2025·0 cites·26 claims
- 2258US6240532B1Programmable hit and write policy for cache memory testRISE TECHNOLOGY COMPANY·Filed 1998·Granted May 29, 2001·23 cites·29 claims
- 2355US6865633B2Independent reset of arbiters and agents to allow for delayed agent resetBROADCOM CORP·Filed 2003·Granted Mar 8, 2005·3 cites·19 claims
- 2453US6321300B1Apparatus and method for dynamically reconfigurable timed flushing of a queue of coalescing write buffersRISE TECHNOLOGY COMPANY·Filed 1999·Granted Nov 20, 2001·26 cites·23 claims
- 2552US7076582B2Bus precharge during a phase of a clock signal to eliminate idle clock cycleBROADCOM CORP·Filed 2004·Granted Jul 11, 2006·2 cites·15 claims
- 2652US2024211259A1Prefetching with saturation controlAKEANA INC·Filed 2023·Application pending·0 cites
- 2734US2005193290A1Built-in self test method and apparatus for jitter transfer, jitter tolerance, and FIFO data bufferFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →