Inventor · disambiguated record
Jackson L. Ellis
Also filed as: ELLIS JACKSON · ELLIS JACKSON L · ELLIS JACKSON LLOYD
49 granted patents·12 pending applications·1,052 citations·filing 1990–2025
98Inventor score
Files withLSI LOGIC CORP14SEAGATE TECHNOLOGY LLC14LSI CORP7INTEL CORP6SK HYNIX NAND PRODUCT SOLUTIONS CORP5
Top patents by PatentIndex Score
61 records- 0192US10140215B1Low overhead mapping for highly sequential dataSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Nov 27, 2018·9 cites·20 claims
- 0291US6336150B1Apparatus and method for enhancing data transfer rates using transfer control blocksLSI LOGIC CORP·Filed 1998·Granted Jan 1, 2002·134 cites·16 claims
- 0389US8339891B2Power savings and/or dynamic power management in a memoryARNTZEN ESKILD T·Filed 2010·Granted Dec 25, 2012·21 cites·18 claims
- 0487US10481205B2Robust secure testing of integrated circuitsSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Nov 19, 2019·4 cites·18 claims
- 0587US6081849AMethod and structure for switching multiple contexts in storage subsystem target deviceLSI LOGIC CORP·Filed 1996·Granted Jun 27, 2000·145 cites·20 claims
- 0686US6617893B1Digital variable clock dividerLSI LOGIC CORP·Filed 1998·Granted Sep 9, 2003·49 cites·20 claims
- 0785US12112055B2Erasure coding write hole closure for solid-state drive (SSD) erasure codingINTEL CORP·Filed 2020·Granted Oct 8, 2024·2 cites·15 claims
- 0885US11971782B2On-SSD erasure coding with uni-directional commandsSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2020·Granted Apr 30, 2024·2 cites·19 claims
- 0985US7461183B2Method of processing a context for executionLSI CORP·Filed 2004·Granted Dec 2, 2008·45 cites·24 claims
- 1084US6029226AMethod and apparatus having automated write data transfer with optional skip by processing two write commands as a single write commandLSI LOGIC CORP·Filed 1996·Granted Feb 22, 2000·126 cites·8 claims
- 1182US12260126B2SSD managed host write atomicity with arbitrary transfer lengthSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2024·Granted Mar 25, 2025·0 cites·20 claims
- 1281US12019910B2SSD managed host write atomicity with arbitrary transfer lengthSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2020·Granted Jun 25, 2024·1 cites·17 claims
- 1381US10126964B2Hardware based map acceleration using forward and reverse cache tablesSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Nov 13, 2018·3 cites·20 claims
- 1481US6449666B2One retrieval channel in a data controller having staging registers and a next pointer register and programming a context of a direct memory access blockLSI LOGIC CORP·Filed 1998·Granted Sep 10, 2002·66 cites·1 claims
- 1581US6247040B1Method and structure for automated switching between multiple contexts in a storage subsystem target deviceLSI LOGIC CORP·Filed 1996·Granted Jun 12, 2001·103 cites·22 claims
- 1680US10484371B2Device controller security systemSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Nov 19, 2019·3 cites·19 claims
- 1780US8842480B2Automated control of opening and closing of synchronous dynamic random access memory rowsELLIS JACKSON L·Filed 2012·Granted Sep 23, 2014·11 cites·21 claims
- 1878US6324594B1System for transferring data having a generator for generating a plurality of transfer extend entries in response to a plurality of commands receivedLSI LOGIC CORP·Filed 1998·Granted Nov 27, 2001·61 cites·17 claims
- 1977US12430208B2ON-SSD erasure coding with uni-directional commandsSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2024·Granted Sep 30, 2025·0 cites·27 claims
- 2076US5907717ACross-connected memory system for allocating pool buffers in each frame buffer and providing addresses thereofLSI LOGIC CORP·Filed 1996·Granted May 25, 1999·93 cites·8 claims
- 2176US2025199723A1Ssd managed host write atomicity with arbitrary transfer lengthSK HYNIX NAND PRODUCT SOLUTIONS CORP·Filed 2025·Application pending·0 cites
- 2275US9250995B2Protection of data in memorySEAGATE TECHNOLOGY LLC·Filed 2013·Granted Feb 2, 2016·4 cites·20 claims
- 2375US7809899B2System for integrity protection for standard 2n-bit multiple sized memory devicesLSI CORP·Filed 2007·Granted Oct 5, 2010·3 cites·20 claims
- 2472US8806112B2Meta data handling within a flash media controllerSOMANACHE VINAY ASHOK·Filed 2011·Granted Aug 12, 2014·6 cites·15 claims
- 2570US8285892B2Quantum burst arbiter and memory controllerARNTZEN ESKILD T·Filed 2010·Granted Oct 9, 2012·4 cites·18 claims
- 2670US7596639B2Skip mask table automated context generationLSI CORP·Filed 2004·Granted Sep 29, 2009·17 cites·39 claims
- 2769US8412870B2Optimized arbiter using multi-level arbitrationFREDENBERG SHERI L·Filed 2010·Granted Apr 2, 2013·5 cites·19 claims
- 2865US11630779B2Hybrid storage device with three-level memory mappingSEAGATE TECHNOLOGY LLC·Filed 2021·Granted Apr 18, 2023·0 cites·20 claims
- 2960US10754555B2Low overhead mapping for highly sequential dataSEAGATE TECHNOLOGY LLC·Filed 2018·Granted Aug 25, 2020·0 cites·23 claims
- 3058US8645618B2Flexible flash commandsSOMANACHE VINAY ASHOK·Filed 2011·Granted Feb 4, 2014·1 cites·20 claims
- 3158US7613856B2Arbitrating access for a plurality of data channel inputs with different characteristicsLSI CORP·Filed 2004·Granted Nov 3, 2009·7 cites·13 claims
- 3258US7181548B2Command queueing engineLSI LOGIC CORP·Filed 1998·Granted Feb 20, 2007·23 cites·11 claims
- 3357US8996942B2Suspend SDRAM refresh cycles during normal DDR operationLSI CORP·Filed 2013·Granted Mar 31, 2015·2 cites·20 claims
- 3457US8006001B2Method and apparatus for manipulating direct memory access transfersLSI CORP·Filed 2004·Granted Aug 23, 2011·5 cites·22 claims
- 3556US2024111459A1Storage command comprising time parameterINTEL CORP·Filed 2023·Application pending·0 cites
- 3655US7574541B2FIFO sub-system with in-line correctionLSI LOGIC CORP·Filed 2004·Granted Aug 11, 2009·5 cites·8 claims
- 3755US2025036783A1Network interface device-based memory access to reduce write amplification factor and provide attestationINTEL CORP·Filed 2024·Application pending·0 cites
- 3854US7334056B2Scalable architecture for context executionLSI LOGIC CORP·Filed 2004·Granted Feb 19, 2008·4 cites·14 claims
- 3953US2024329873A1Management of buffer utilizationINTEL CORP·Filed 2024·Application pending·0 cites
- 4052US11221956B2Hybrid storage device with three-level memory mappingSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Jan 11, 2022·0 cites·11 claims
- 4152US10783119B2Fixed record media conversion with data compression and encryptionSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Sep 22, 2020·0 cites·20 claims
- 4252US2024211392A1Buffer allocationINTEL CORP·Filed 2024·Application pending·0 cites
- 4350US10248330B2Data storage device with buffer tenure managementSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Apr 2, 2019·0 cites·19 claims
- 4450US2024264959A1Doorbell register injection rate managementELLIS JACKSON L·Filed 2024·Application pending·0 cites
- 4547US10740251B2Hybrid drive translation layerSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Aug 11, 2020·0 cites·20 claims
- 4647US5420994AMethod for reading a multiple byte data element in a memory system with at least one cache and a main memoryNCR CORP·Filed 1990·Granted May 30, 1995·21 cites·15 claims
- 4746US2020089537A1Apparatus and method for bandwidth allocation and quality of service management in a storage device shared by multiple tenantsINTEL CORP·Filed 2019·Application pending·0 cites
- 4844US10635581B2Hybrid drive garbage collectionSEAGATE TECHNOLOGY LLC·Filed 2017·Granted Apr 28, 2020·0 cites·19 claims
- 4944US5434990AMethod for serially or concurrently addressing n individually addressable memories each having an address latch and data latchNCR CORP·Filed 1990·Granted Jul 18, 1995·11 cites·4 claims
- 5041US6148326AMethod and structure for independent disk and host transfer in a storage subsystem target deviceLSI LOGIC CORP·Filed 1996·Granted Nov 14, 2000·13 cites·6 claims
Showing the top 50 of 61 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Jackson L. Ellis files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →