Inventor · disambiguated record
Javier Soto Gonzalez
Also filed as: GONZALEZ JAVIER S · GONZALEZ JAVIER SOTO
15 granted patents·1 pending application·214 citations·filing 2008–2019
93Inventor score
Top patents by PatentIndex Score
16 records- 0197US9559088B2Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the sameGONZALEZ JAVIER SOTO·Filed 2014·Granted Jan 31, 2017·52 cites·6 claims
- 0296US8736065B2Multi-chip package having a substrate with a plurality of vertically embedded die and a process of forming the sameGONZALEZ JAVIER SOTO·Filed 2010·Granted May 27, 2014·38 cites·15 claims
- 0396US8618652B2Forming functionalized carrier structures with coreless packagesNALLA RAVI K·Filed 2010·Granted Dec 31, 2013·30 cites·15 claims
- 0494US8421245B2Substrate with embedded stacked through-silicon via dieGONZALEZ JAVIER SOTO·Filed 2010·Granted Apr 16, 2013·19 cites·15 claims
- 0591US9000599B2Multichip integration with through silicon via (TSV) die embedded in packageRAORANE DIGVIJAY A·Filed 2013·Granted Apr 7, 2015·14 cites·13 claims
- 0691US8901724B2Semiconductor package with embedded die and its methods of fabricationGUZEK JOHN STEPHEN·Filed 2009·Granted Dec 2, 2014·28 cites·7 claims
- 0789US8786066B2Die-stacking using through-silicon vias on bumpless build-up layer substrates including embedded-dice, and processes of forming sameGUZEK JOHN S·Filed 2010·Granted Jul 22, 2014·11 cites·36 claims
- 0887US8466559B2Forming die backside coating structures with coreless packagesMANEPALLI RAHUL N·Filed 2010·Granted Jun 18, 2013·9 cites·17 claims
- 0983US9716084B2Multichip integration with through silicon via (TSV) die embedded in packageINTEL CORP·Filed 2016·Granted Jul 25, 2017·3 cites·10 claims
- 1078US7952182B2Semiconductor device with package to package connectionINTEL CORP·Filed 2008·Granted May 31, 2011·8 cites·18 claims
- 1165US9397079B2Multichip integration with through silicon via (TSV) die embedded in packageINTEL CORP·Filed 2015·Granted Jul 19, 2016·1 cites·10 claims
- 1261US11107766B2Substrate with embedded stacked through-silicon via dieINTEL CORP·Filed 2019·Granted Aug 31, 2021·0 cites·14 claims
- 1361US8987065B2Forming functionalized carrier structures with coreless packagesINTEL CORP·Filed 2013·Granted Mar 24, 2015·1 cites·5 claims
- 1453US10461032B2Substrate with embedded stacked through-silicon via dieINTEL CORP·Filed 2013·Granted Oct 29, 2019·0 cites·7 claims
- 1552US9257380B2Forming functionalized carrier structures with coreless packagesINTEL CORP·Filed 2015·Granted Feb 9, 2016·0 cites·18 claims
- 1648US2009321932A1Coreless substrate package with symmetric external dielectric layersGONZALEZ JAVIER SOTO·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →