Inventor · disambiguated record
James Hadley
Also filed as: HADLEY JAMES · HADLEY JAMES D
12 granted patents·3 pending applications·87 citations·filing 1999–2019
89Inventor score
Technology areasG06F
Top patents by PatentIndex Score
15 records- 0183US11126438B2System, apparatus and method for a hybrid reservation station for a processorINTEL CORP·Filed 2019·Granted Sep 21, 2021·4 cites·17 claims
- 0279US9182986B2Copy-on-write buffer for restoring program code from a speculative region to a non-speculative regionRAJWAR RAVI·Filed 2012·Granted Nov 10, 2015·7 cites·28 claims
- 0377US8438369B2Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessorMARDEN MORRIS·Filed 2010·Granted May 7, 2013·4 cites·13 claims
- 0471US6609193B1Method and apparatus for multi-thread pipelined instruction decoderINTEL CORP·Filed 1999·Granted Aug 19, 2003·54 cites·36 claims
- 0570US8521993B2Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessorMARDEN MORRIS·Filed 2007·Granted Aug 27, 2013·4 cites·4 claims
- 0663US9524191B2Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elementsMARDEN MORRIS·Filed 2010·Granted Dec 20, 2016·1 cites·12 claims
- 0763US6931516B2Pipelined instruction decoder for multi-threaded processorsINTEL CORP·Filed 2003·Granted Aug 16, 2005·9 cites·15 claims
- 0862US9292288B2Systems and methods for flag tracking in move elimination operationsKADGI VIJAYKUMAR B·Filed 2013·Granted Mar 22, 2016·2 cites·20 claims
- 0959US8402253B2Managing multiple threads in a single pipelineMERTEN MATTHEW·Filed 2006·Granted Mar 19, 2013·2 cites·18 claims
- 1056US2017161106A1Providing thread fairness in a hyper-threaded microprocessorINTEL CORP·Filed 2016·Application pending·0 cites
- 1149US8504804B2Managing multiple threads in a single pipelineMERTEN MATTHEW·Filed 2012·Granted Aug 6, 2013·0 cites·20 claims
- 1242US9733939B2Physical reference list for tracking physical register sharingINTEL CORP·Filed 2012·Granted Aug 15, 2017·0 cites·22 claims
- 1342US2007043934A1Early misprediction recovery through periodic checkpointsINTEL CORP·Filed 2005·Application pending·0 cites
- 1440US10235180B2Scheduler implementing dependency matrix having restricted entriesSRINIVASAN SRIKANTH T·Filed 2012·Granted Mar 19, 2019·0 cites·7 claims
- 1535US2014095814A1Memory Renaming Mechanism in MicroarchitectureMARDEN MORRIS·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →