Providing thread fairness in a hyper-threaded microprocessor

Abstract

A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

What is claimed is: 
     
         1 . An apparatus comprising:
 an execution unit to execute a plurality of instructions;   a reservation unit coupled to the execution unit, wherein the reservation unit is to hold instruction information associated with the plurality of instructions in a plurality of reservation entries; and   a first storage element to include a first mask field associated with a first number reservation entries of the plurality of reservation entries, the first mask field, when holding a first value, to indicate the first number of reservation entries are associated with a first processing element.   
     
     
         2 . The apparatus of  claim 1 , wherein the first processing element is selected from a group consisting of a thread, a logical processor, and a core. 
     
     
         3 . The apparatus of  claim 1 , wherein instruction information includes a plurality of information elements, wherein each of the plurality of information elements are selected from a group consisting of dependency information, instruction identification information, result information, and scheduling information. 
     
     
         4 . The apparatus of  claim 1 , wherein the first number of entries is an even number of entries. 
     
     
         5 . The apparatus of  claim 1 , further comprising a second storage element to include a second mask field associated with the first number of reservation entries, wherein
 when the first mask field holds the first value and the second mask field holds the first value, the first number of reservation entries are associated with the first processing element and a second processing element;   when the first mask field holds the first value and the second mask field holds the second value, the first number of reservation entries are associated with the first processing element and not with the second processing element;   when the first mask field holds the second value and the second mask field holds the second value, the first number of reservation entries are not associated with the first processing element and are not associated with the second processing element; and   when the first mask field holds the second value and the second mask field holds the first value, the first number of reservation entries are associated with the second processing element and not with the first processing element.   
     
     
         6 . The apparatus of  claim 1 , wherein the first and second storage elements are registers.