Inventor · disambiguated record
Alexandre J. Farcy
Also filed as: FARCY ALEXANDRE · FARCY ALEXANDRE J
30 granted patents·7 pending applications·65 citations·filing 2003–2021
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
37 records- 0190US10409612B2Apparatus and method for transactional memory and lock elision including an abort instruction to abort speculative executionINTEL CORP·Filed 2015·Granted Sep 10, 2019·7 cites·20 claims
- 0286US11106461B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2018·Granted Aug 31, 2021·2 cites·24 claims
- 0384US9940131B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Apr 10, 2018·4 cites·28 claims
- 0484US9940130B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Apr 10, 2018·4 cites·22 claims
- 0584US9916160B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2014·Granted Mar 13, 2018·4 cites·20 claims
- 0681US9164762B2Rotate instructions that complete execution without reading carry flagINTEL CORP·Filed 2013·Granted Oct 20, 2015·4 cites·31 claims
- 0779US8738893B2Add instructions to add three source operandsINTEL CORP·Filed 2013·Granted May 27, 2014·5 cites·20 claims
- 0877US8549264B2Add instructions to add three source operandsGOPAL VINODH·Filed 2009·Granted Oct 1, 2013·6 cites·30 claims
- 0977US8504807B2Rotate instructions that complete execution without reading carry flagGOPAL VINODH·Filed 2009·Granted Aug 6, 2013·4 cites·22 claims
- 1077US8438369B2Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessorMARDEN MORRIS·Filed 2010·Granted May 7, 2013·4 cites·13 claims
- 1175US11900108B2Rotate instructions that complete execution either without writing or reading flagsINTEL CORP·Filed 2021·Granted Feb 13, 2024·0 cites·19 claims
- 1270US8521993B2Providing thread fairness by biasing selection away from a stalling thread using a stall-cycle counter in a hyper-threaded microprocessorMARDEN MORRIS·Filed 2007·Granted Aug 27, 2013·4 cites·4 claims
- 1364US9280492B2System and method for a load instruction with code conversion having access permissions to indicate failure of load content from registersINTEL CORP·Filed 2013·Granted Mar 8, 2016·1 cites·20 claims
- 1464US7913064B2Operation frame filtering, building, and executionINTEL CORP·Filed 2009·Granted Mar 22, 2011·2 cites·18 claims
- 1563US9524191B2Apparatus including a stall counter to bias processing element selection, and masks to allocate reservation unit entries to one or more processing elementsMARDEN MORRIS·Filed 2010·Granted Dec 20, 2016·1 cites·12 claims
- 1663US7533247B2Operation frame filtering, building, and executionINTEL CORP·Filed 2005·Granted May 12, 2009·2 cites·19 claims
- 1761US9348591B2Multi-level tracking of in-use state of cache linesKIM ILHYUN·Filed 2011·Granted May 24, 2016·2 cites·14 claims
- 1860US9990201B2Multiplication instruction for which execution completes without writing a carry flagGOPAL VINODH·Filed 2009·Granted Jun 5, 2018·1 cites·32 claims
- 1960US9354875B2Enhanced loop streaming detector to drive logic optimizationMERTEN MATTHEW C·Filed 2012·Granted May 31, 2016·2 cites·15 claims
- 2059US10649774B2Multiplication instruction for which execution completes without writing a carry flagINTEL CORP·Filed 2017·Granted May 12, 2020·0 cites·23 claims
- 2159US8402253B2Managing multiple threads in a single pipelineMERTEN MATTHEW·Filed 2006·Granted Mar 19, 2013·2 cites·18 claims
- 2256US8825989B2Technique to perform three-source operationsINTEL CORP·Filed 2013·Granted Sep 2, 2014·0 cites·19 claims
- 2356US2017161106A1Providing thread fairness in a hyper-threaded microprocessorINTEL CORP·Filed 2016·Application pending·0 cites
- 2454US10409611B2Apparatus and method for transactional memory and lock elision including abort and end instructions to abort or commit speculative executionINTEL CORP·Filed 2015·Granted Sep 10, 2019·0 cites·20 claims
- 2553US7797683B2Decoupling the number of logical threads from the number of simultaneous physical threads in a processorINTEL CORP·Filed 2003·Granted Sep 14, 2010·4 cites·16 claims
- 2650US2014059333A1Method, apparatus, and system for speculative abort control mechanismsDIXON MARTIN G·Filed 2012·Application pending·0 cites
- 2749US8504804B2Managing multiple threads in a single pipelineMERTEN MATTHEW·Filed 2012·Granted Aug 6, 2013·0 cites·20 claims
- 2845US7562206B2Multilevel scheme for dynamically and statically predicting instruction resource utilization to generate execution cluster partitionsINTEL CORP·Filed 2005·Granted Jul 14, 2009·0 cites·14 claims
- 2945US2005149912A1Dynamic online optimizerINTEL CORP·Filed 2003·Application pending·0 cites
- 3044US8589663B2Technique to perform three-source operationsSODANI AVINASH·Filed 2006·Granted Nov 19, 2013·0 cites·19 claims
- 3144US7475225B2Method and apparatus for microarchitecture partitioning of execution clustersINTEL CORP·Filed 2005·Granted Jan 6, 2009·0 cites·12 claims
- 3243US2005149696A1Method and apparatus to control steering of instruction streamsFiled 2003·Application pending·0 cites
- 3342US2015032998A1Method, apparatus, and system for transactional speculation control instructionsRAJWAR RAVI·Filed 2012·Application pending·0 cites
- 3441US8291196B2Forward-pass dead instruction identification and removal at run-timeJOURDAN STEPHAN J·Filed 2005·Granted Oct 16, 2012·0 cites·12 claims
- 3540US2008065865A1In-use bits for efficient instruction fetch operationsKIM ILHYUN·Filed 2006·Application pending·0 cites
- 3638US9158696B2Hiding instruction cache miss latency by running tag lookups ahead of the instruction accessesKIM ILHYUN·Filed 2011·Granted Oct 13, 2015·0 cites·21 claims
- 3733US2014195790A1Processor with second jump execution unit for branch mispredictionMERTEN MATTHEW C·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →