Inventor · disambiguated record
Jagjot Kaur
Also filed as: KAUR JAGJOT
5 granted patents·17 citations·filing 2016–2022
73Inventor score
Files withCADENCE DESIGN SYSTEMS INC5
Top patents by PatentIndex Score
5 records- 0188US11409931B1Systems and methods for optimizing scan pipelining in hierarchical test designCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Aug 9, 2022·3 cites·20 claims
- 0285US10417363B1Power and scan resource reduction in integrated circuit designs having shift registersCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 17, 2019·6 cites·14 claims
- 0381US10740515B1Devices and methods for test point insertion coverageCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Aug 11, 2020·6 cites·20 claims
- 0471US10234504B1Optimizing core wrappers in an integrated circuitCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Mar 19, 2019·2 cites·16 claims
- 0547US12488176B1Systems and methods for reducing test point power consumption in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2022·Granted Dec 2, 2025·0 cites·14 claims
Join the waitlist — get patent alerts
Get an alert when Jagjot Kaur files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →