Inventor · disambiguated record
Janet L. Olson
Also filed as: OLSON JANET · OLSON JANET L
10 granted patents·206 citations·filing 1996–2017
90Inventor score
Files withSYNOPSYS INC10
Top patents by PatentIndex Score
10 records- 0187US10372858B2Design-for-testability (DFT) insertion at register-transfer-level (RTL)SYNOPSYS INC·Filed 2017·Granted Aug 6, 2019·7 cites·14 claims
- 0285US9697314B1Identifying and using slices in an integrated circuit (IC) designSYNOPSYS INC·Filed 2016·Granted Jul 4, 2017·6 cites·15 claims
- 0385US9652573B1Creating and using a wide-gate data structure to represent a wide-gate in an integrated circuit (IC) designSYNOPSYS INC·Filed 2016·Granted May 16, 2017·6 cites·12 claims
- 0481US9690890B1Creating and using a wide-bus data structure to represent a wide-bus in an integrated circuit (IC) designSYNOPSYS INC·Filed 2016·Granted Jun 27, 2017·4 cites·12 claims
- 0567US6480815B1Path dependent power modelingSYNOPSYS INC·Filed 1999·Granted Nov 12, 2002·47 cites·13 claims
- 0665US5903476AThree-dimensional power modeling table having dual output capacitance indicesSYNOPSYS INC·Filed 1996·Granted May 11, 1999·45 cites·20 claims
- 0760US6195630B1Three-dimensional power modeling table having dual output capacitance indicesSYNOPSYS INC·Filed 1999·Granted Feb 27, 2001·23 cites·5 claims
- 0859US5838579AState dependent power modelingSYNOPSYS INC·Filed 1996·Granted Nov 17, 1998·43 cites·23 claims
- 0953US5949689APath dependent power modelingSYNOPSYS INC·Filed 1996·Granted Sep 7, 1999·25 cites·20 claims
- 1038US10354032B2Optimizing an integrated circuit (IC) design comprising at least one wide-gate or wide-busSYNOPSYS INC·Filed 2016·Granted Jul 16, 2019·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →