Inventor · disambiguated record
James R. Torossian
Also filed as: TOROSSIAN JAMES R
11 granted patents·1 pending application·656 citations·filing 1999–2016
92Inventor score
Technology areasG06F
Files withSYNOPSYS INC4VAST SYSTEMS TECHNOLOGY CORP4CLARK NEVILLE A2HELLESTRAND GRAHAM R1VAST SYSTEMS TECHNOLOGY INC1
Top patents by PatentIndex Score
12 records- 0195US6751583B1Hardware and software co-simulation including simulating a target processor using binary translationVAST SYSTEMS TECHNOLOGY CORP·Filed 2001·Granted Jun 15, 2004·199 cites·83 claims
- 0292US6263302B1Hardware and software co-simulation including simulating the cache of a target processorVAST SYSTEMS TECHNOLOGY CORP·Filed 2000·Granted Jul 17, 2001·196 cites·86 claims
- 0388US8463589B2Modifying a virtual processor model for hardware/software simulationCLARK NEVILLE A·Filed 2007·Granted Jun 11, 2013·24 cites·33 claims
- 0487US6584436B2Hardware and software co-simulation including executing an analyzed user programVAST SYSTEMS TECHNOLOGY INC·Filed 2001·Granted Jun 24, 2003·71 cites·19 claims
- 0585US10360327B2Modifying a virtual processor model for hardware/software simulationSYNOPSYS INC·Filed 2015·Granted Jul 23, 2019·4 cites·20 claims
- 0685US6230114B1Hardware and software co-simulation including executing an analyzed user programVAST SYSTEMS TECHNOLOGY CORP·Filed 1999·Granted May 8, 2001·134 cites·71 claims
- 0783US9058447B2Modifying a virtual processor model for hardware/software simulationSYNOPSYS INC·Filed 2013·Granted Jun 16, 2015·6 cites·20 claims
- 0882US7567893B2Clock simulation system and methodVAST SYSTEMS TECHNOLOGY CORP·Filed 2005·Granted Jul 28, 2009·14 cites·39 claims
- 0974US9311437B2Modeling a bus for a system design incorporating one or more programmable processorsSYNOPSYS INC·Filed 2014·Granted Apr 12, 2016·3 cites·20 claims
- 1070US8644305B2Method and system for modeling a bus for a system design incorporating one or more programmable processorsCLARK NEVILLE A·Filed 2008·Granted Feb 4, 2014·5 cites·23 claims
- 1142US10409935B2Modeling a bus for a system design incorporating one or more programmable processorsSYNOPSYS INC·Filed 2016·Granted Sep 10, 2019·0 cites·17 claims
- 1236US2002019969A1Hardware and software co-simulation including simulating the cache of a target processorHELLESTRAND GRAHAM R·Filed 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →