Inventor · disambiguated record
Jami A. Wiedemer
Also filed as: WIEDEMER JAMI · WIEDEMER JAMI A
4 granted patents·15 pending applications·2 citations·filing 2013–2023
61Inventor score
Files withINTEL CORP19
Top patents by PatentIndex Score
19 records- 0176US2023253499A1Diffused tip extension transistorINTEL CORP·Filed 2023·Application pending·0 cites
- 0270US11664452B2Diffused tip extension transistorINTEL CORP·Filed 2020·Granted May 30, 2023·0 cites·20 claims
- 0363US10872977B2Diffused tip extension transistorINTEL CORP·Filed 2019·Granted Dec 22, 2020·0 cites·20 claims
- 0458US11264517B2CMOS varactor with increased tuning rangeINTEL CORP·Filed 2014·Granted Mar 1, 2022·2 cites·4 claims
- 0556US10304956B2Diffused tip extension transistorINTEL CORP·Filed 2013·Granted May 28, 2019·0 cites·24 claims
- 0653US2024204103A1Transistor gate-channel arrangements with multiple dipole materialsINTEL CORP·Filed 2022·Application pending·0 cites
- 0752US2025113603A1Gate-all-around integrated circuit structures having depopulated channel structures using split source or drain approachesINTEL CORP·Filed 2023·Application pending·0 cites
- 0852US2025212522A1Capping nanoribbon fins in superlattice structures during fabricationINTEL CORP·Filed 2023·Application pending·0 cites
- 0951US2023420460A1Lower device access in stacked transistor devicesINTEL CORP·Filed 2022·Application pending·0 cites
- 1050US2023402513A1Source and drain contacts formed using sacrificial regions of source and drainINTEL CORP·Filed 2022·Application pending·0 cites
- 1150US2024204060A1Nanoribbon stacks without dielectric protection caps for top nanoribbonsINTEL CORP·Filed 2022·Application pending·0 cites
- 1249US2023420528A1Self-aligned embedded source and drain contactsINTEL CORP·Filed 2022·Application pending·0 cites
- 1349US2023402507A1Dual metal silicide for stacked transistor devicesINTEL CORP·Filed 2022·Application pending·0 cites
- 1448US2024222521A1Technologies for ribbon field effect transistors with variable fin numbersINTEL CORP·Filed 2022·Application pending·0 cites
- 1548US2023395718A13d source and drain contacts tuned for vertically stacked pmos and nmosINTEL CORP·Filed 2022·Application pending·0 cites
- 1648US2023395697A1Removal of upper channel bodies in stacked gate-all-around (gaa) device structuresINTEL CORP·Filed 2022·Application pending·0 cites
- 1748US2023395717A13d source and drain contacts tuned for pmos and nmosINTEL CORP·Filed 2022·Application pending·0 cites
- 1848US2023420562A1Diffusion cut stressors for stacked transistorsINTEL CORP·Filed 2022·Application pending·0 cites
- 1947US2024222376A1Technologies for ribbon field effect transistors with variable fin channel dimensionsINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →