Diffused tip extension transistor

Abstract

A method including forming an opening in a junction region of a fin on and extending from a substrate; introducing a doped semiconductor material in the opening; and thermal processing the doped semiconductor material. A method including forming a gate electrode on a fin extending from a substrate; forming openings in the fin adjacent opposite sides of the gate electrode; introducing a doped semiconductor material in the openings; and thermally processing the doped semiconductor material sufficient to induce the diffusion of a dopant in the doped semiconductor material. An apparatus including a gate electrode transversing a fin extending from a substrate; and semiconductor material filled openings in junction regions of the fin adjacent opposite sides of the gate electrode, wherein the semiconductor material comprises a dopant.

What is claimed is: 
     
         1 . An apparatus comprising:
 a three-dimensional semiconductor structure extending from and continuous with a semiconductor substrate, the three-dimensional semiconductor structure having a channel region with rounded edges;   a gate electrode at least partially surrounding the channel region of the three-dimensional semiconductor structure;   semiconductor material filled openings in junction regions of the three-dimensional semiconductor structure adjacent opposite sides of the gate electrode, the semiconductor material filled openings and the three-dimensional semiconductor structure comprising a same semiconductor material, and the semiconductor material filled openings comprising a dopant having a same dopant concentration at a top of the semiconductor material filled openings, at a bottom of the semiconductor material filled openings, and along a height of the semiconductor material filled openings between the bottom and the top of the semiconductor material filled openings; and   a sidewall spacer on each side of the opposite sides of the gate electrode.   
     
     
         2 . The apparatus of  claim 1 , wherein a portion of the three-dimensional semiconductor structure underlying the sidewall spacer comprises the dopant. 
     
     
         3 . The apparatus of  claim 1 , wherein the dopant comprises an N-type dopant. 
     
     
         4 . The apparatus of  claim 1 , wherein the dopant is phosphorous. 
     
     
         5 . The apparatus of  claim 1 , wherein the semiconductor material is silicon. 
     
     
         6 . An apparatus comprising:
 a three-dimensional semiconductor structure extending from and continuous with a semiconductor substrate, the three-dimensional semiconductor structure having a channel region with rounded edges;   a gate electrode at least partially surrounding the channel region of the three-dimensional semiconductor structure; and   semiconductor material filled openings in junction regions of the three-dimensional semiconductor structure adjacent opposite sides of the gate electrode, the semiconductor material filled openings and the three-dimensional semiconductor structure comprising a same semiconductor material, and the semiconductor material filled openings comprising a dopant having a same dopant concentration at a top of the semiconductor material filled openings, at a bottom of the semiconductor material filled openings, and along a height of the semiconductor material filled openings between the bottom and the top of the semiconductor material filled openings.   
     
     
         7 . The apparatus of  claim 6 , wherein a portion of the three-dimensional semiconductor structure comprises the dopant. 
     
     
         8 . The apparatus of  claim 6 , wherein the dopant comprises an N-type dopant. 
     
     
         9 . The apparatus of  claim 6 , wherein the dopant is phosphorous. 
     
     
         10 . The apparatus of  claim 6 , wherein the semiconductor material is silicon. 
     
     
         11 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a three-dimensional semiconductor structure extending from and continuous with a semiconductor substrate, the three-dimensional semiconductor structure having a channel region with rounded edges; 
 a gate electrode at least partially surrounding the channel region of the three-dimensional semiconductor structure; 
 semiconductor material filled openings in junction regions of the three-dimensional semiconductor structure adjacent opposite sides of the gate electrode, the semiconductor material filled openings and the three-dimensional semiconductor structure comprising a same semiconductor material, and the semiconductor material filled openings comprising a dopant having a same dopant concentration at a top of the semiconductor material filled openings, at a bottom of the semiconductor material filled openings, and along a height of the semiconductor material filled openings between the bottom and the top of the semiconductor material filled openings; and 
 a sidewall spacer on each side of the opposite sides of the gate electrode. 
   
     
     
         12 . The computing device of  claim 11 , further comprising:
 a memory coupled to the board.   
     
     
         13 . The computing device of  claim 11 , further comprising:
 a communication chip coupled to the board.   
     
     
         14 . The computing device of  claim 11 , further comprising:
 a camera coupled to the board.   
     
     
         15 . The computing device of  claim 11 , further comprising:
 a battery coupled to the board.   
     
     
         16 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including an integrated circuit structure, comprising:
 a three-dimensional semiconductor structure extending from and continuous with a semiconductor substrate, the three-dimensional semiconductor structure having a channel region with rounded edges; 
 a gate electrode at least partially surrounding the channel region of the three-dimensional semiconductor structure; and 
 semiconductor material filled openings in junction regions of the three-dimensional semiconductor structure adjacent opposite sides of the gate electrode, the semiconductor material filled openings and the three-dimensional semiconductor structure comprising a same semiconductor material, and the semiconductor material filled openings comprising a dopant having a same dopant concentration at a top of the semiconductor material filled openings, at a bottom of the semiconductor material filled openings, and along a height of the semiconductor material filled openings between the bottom and the top of the semiconductor material filled openings. 
   
     
     
         17 . The computing device of  claim 16 , further comprising:
 a memory coupled to the board.   
     
     
         18 . The computing device of  claim 16 , further comprising:
 a communication chip coupled to the board.   
     
     
         19 . The computing device of  claim 16 , further comprising:
 a camera coupled to the board.   
     
     
         20 . The computing device of  claim 16 , further comprising:
 a battery coupled to the board.