Inventor · disambiguated record
Paul Packan
Also filed as: PACKAN PAUL · PACKAN PAUL A
21 granted patents·21 pending applications·1,141 citations·filing 1994–2025
96Inventor score
Top patents by PatentIndex Score
42 records- 0197US5908313AMethod of forming a transistorINTEL CORP·Filed 1996·Granted Jun 1, 1999·297 cites·16 claims
- 0296US7682916B2Field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2008·Granted Mar 23, 2010·31 cites·10 claims
- 0396US7338873B2Method of fabricating a field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2006·Granted Mar 4, 2008·28 cites·5 claims
- 0496US6887762B1Method of fabricating a field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 1999·Granted May 3, 2005·141 cites·10 claims
- 0595US5710450ATransistor with ultra shallow tip and method of fabricationINTEL CORP·Filed 1994·Granted Jan 20, 1998·199 cites·30 claims
- 0694US6326664B1Transistor with ultra shallow tip and method of fabricationINTEL CORP·Filed 1997·Granted Dec 4, 2001·128 cites·33 claims
- 0791US7436035B2Method of fabricating a field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2004·Granted Oct 14, 2008·36 cites·7 claims
- 0887US6198142B1Transistor with minimal junction capacitance and method of fabricationINTEL CORP·Filed 1998·Granted Mar 6, 2001·85 cites·9 claims
- 0985US9793373B2Field effect transistor structure with abrupt source/drain junctionsINTEL CORP·Filed 2017·Granted Oct 17, 2017·2 cites·10 claims
- 1084US9640634B2Field effect transistor structure with abrupt source/drain junctionsMURTHY ANAND S·Filed 2010·Granted May 2, 2017·4 cites·16 claims
- 1184US6020244AChannel dopant implantation with automatic compensation for variations in critical dimensionINTEL CORP·Filed 1996·Granted Feb 1, 2000·75 cites·10 claims
- 1279US6800887B1Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2003·Granted Oct 5, 2004·17 cites·5 claims
- 1378US5976939ALow damage doping technique for self-aligned source and drain regionsINTEL CORP·Filed 1995·Granted Nov 2, 1999·54 cites·4 claims
- 1476US7312485B2CMOS fabrication process utilizing special transistor orientationINTEL CORP·Filed 2000·Granted Dec 25, 2007·21 cites·11 claims
- 1576US2023253499A1Diffused tip extension transistorINTEL CORP·Filed 2023·Application pending·0 cites
- 1673US7226824B2Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2004·Granted Jun 5, 2007·11 cites·11 claims
- 1770US11664452B2Diffused tip extension transistorINTEL CORP·Filed 2020·Granted May 30, 2023·0 cites·20 claims
- 1870US7888710B2CMOS fabrication process utilizing special transistor orientationINTEL CORP·Filed 2007·Granted Feb 15, 2011·3 cites·12 claims
- 1970US2025323127A1Integrated circuit structure with deep via bar width tuningINTEL CORP·Filed 2025·Application pending·0 cites
- 2065US7187057B2Nitrogen controlled growth of dislocation loop in stress enhanced transistorINTEL CORP·Filed 2004·Granted Mar 6, 2007·7 cites·12 claims
- 2165US2025112120A1Integrated circuit structure with deep via bar width tuningINTEL CORP·Filed 2023·Application pending·0 cites
- 2263US10872977B2Diffused tip extension transistorINTEL CORP·Filed 2019·Granted Dec 22, 2020·0 cites·20 claims
- 2360US2025311273A1Zero diffusion break for improving transistor densityINTEL CORP·Filed 2024·Application pending·0 cites
- 2458US11264517B2CMOS varactor with increased tuning rangeINTEL CORP·Filed 2014·Granted Mar 1, 2022·2 cites·4 claims
- 2557US2025311427A1Deep via backside (dvb) partial recess for capacitance reduction in complementary fet (cfet) transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 2656US10304956B2Diffused tip extension transistorINTEL CORP·Filed 2013·Granted May 28, 2019·0 cites·24 claims
- 2756US2025393250A1Integrated circuit structures having hybrid channel layoutINTEL CORP·Filed 2024·Application pending·0 cites
- 2855US2025311363A1Backside gate cut formationINTEL CORP·Filed 2024·Application pending·0 cites
- 2955US2025311283A1Selective channel width scaling using implantsINTEL CORP·Filed 2024·Application pending·0 cites
- 3053US2025194179A1Integrated circuit structures with backside contacts and asymmetric source and drain regionsCHU TAO·Filed 2023·Application pending·0 cites
- 3153US2025169130A1Integrated circuit structures with different nanoribbon thicknessesINTEL CORP·Filed 2023·Application pending·0 cites
- 3253US2025113586A1Nbti reduction and reliability improvement for selective layoutsINTEL CORP·Filed 2023·Application pending·0 cites
- 3352US2025113595A1Multiple voltage threshold integrated circuit structure with local layout effect tuningINTEL CORP·Filed 2023·Application pending·0 cites
- 3452US2025107175A1Integrated circuit structures having reduced local layout effectsINTEL CORP·Filed 2023·Application pending·0 cites
- 3551US2025194070A1Integrated circuit structures with transistor gate-channel arrangements for static random-access memoryCHU TAO·Filed 2023·Application pending·0 cites
- 3650US2025006734A1Performance optimization of transistors sharing channel structures of varying widthINTEL CORP·Filed 2023·Application pending·0 cites
- 3750US2024321887A1Integrated circuit device with reduced n-p boundary effectINTEL CORP·Filed 2023·Application pending·0 cites
- 3850US2025203975A1Integrated circuit device with semiconductor structure extending across gate in isolaton regionXU GUOWEI·Filed 2023·Application pending·0 cites
- 3950US2024321859A1Integrated circuit device with performance-enhancing layoutINTEL CORP·Filed 2023·Application pending·0 cites
- 4045US2023317594A1Device performance tuning by deep trench via (dvb) proximity effect in architecture of backside power deliveryCHU TAO·Filed 2022·Application pending·0 cites
- 4144US2024113118A1Ultra-low voltage transistor cell design using gate cut layoutINTEL CORP·Filed 2022·Application pending·0 cites
- 4236US2009323235A1High voltage compliant apparatus for semiconductor fabrication process charging protectionPAE SANGWOO·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →